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Data Path Interface (DPI) to UTOPIA Level 1 Header Translation Device

IDT77V012
SRAM 64K x 32 to 256K x 32 DPI Receive IDT77V012 UTOPIA 1 to DPI interface w/ Header Translation IDT77V400 Switching Memory
OC-3 or STS-3
UTOPIA 1 Receive IDT77155 PHY UTOPIA 1 Transmit Utility Bus
" " " "
Figure 1 Typical IDT77V012 Application with the IDT77V400 Switching Memory
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2001 Integrated Device Technology, Inc.
QRLWSLUFVH'
DPI Transmit " " " "
8, 12, 24, 28 or 32-bit ATM header lookup. Ideal for network side of SwitchStar DSLAM designs where full header access is needed Supports VPI Tunneling Supports both UNI and NNI formats Accounting functionality counts the number of cells on a per VC basis 8-bit UTOPIA Level 1 Tx and Rx interfaces Supports UTOPIA Level 1 cell mode operation 4-bit DPI Tx and Rx interfaces DPI interface supports cell sizes from 52 to 56 bytes for applications requiring a TAG DPI interface operates up to 66MHz In-StreamTM (In-band) programming for configuration of the 77V012, PHY and external search SRAM Supports up to 8K active connections with an external 128K x 32 SRAM. Up to 16K connections are supported in a 256K x 32 SRAM Inserts new ATM cell header and up to four bytes of TAG in receive direction, and removes TAG from cell header in transmit direction
Utility bus interface for programming PHY devices Single +3.3V 0.3V power supply required Inputs are +5.0V tolerant
PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO%
WVL/ VHUXWDH)

The IDT77V012 provides full header translation functionality along with Data Path Interface (DPI) to UTOPIA Level 1 translation for switch and DSLAM designs using the IDT SwitchStar. The address search and replacement algorithm is performed using a VPI Tunneling or Full Header format on 8, 12, 24, 28 or 32-bits of the header. This added flexibility makes it suitable for both UNI and NNI formats. External memory is required to perform the header translation (receive direction only), which will support up to 16K connections using a 256K x 32 SRAM. The new header, which is obtained as a result of the search, can be used to overwrite the existing cell header in the receive path. A four byte TAG can also be added to aid in routing cells. The 77V012 also contains cell counters in the transmit and receive direction. The counters can be used to provide detailed per VC accounting information for a particular port. Other features include In-StreamTM programming, which can be utilized on either the DPI or UTOPIA interfaces, a Utility Bus interface for accessing registers in the PHY device, and an interface for an EEPROM.
5347drw01
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DSC 5347/7
IDT77V012
INDEX
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND RCLK R xLED RENB GND RCLAV RxDATA[0] RxDATA[1] RxDATA[2] VCC RxDATA[3] RxDATA[4] RxDATA[5] RxDATA[6] RxDATA[7] RSOC TCLAV VCC GND TCLK TxLED TENB TxDATA[0] TxDATA[1] TxDATA[2] TxDATA[3] TxDATA[4] GND VCC TxDATA[5] TxDATA[6] TxDATA[7] TxPRTY TSOC CNTRL_A VCC
VCC DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] ADDR[16] GND VCC ADDR[15] ADDR[14] ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ADSP OE GW SCLK GND VCC ADDR[17] CE ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] DATA[16] GND
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
QRLWDUXJLIQR& QL3 QRLWDUXJLIQR& QL3 QRLWDUXJLIQR& QL3 QRLWDUXJLIQR& QL3
PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO%
DPI Transmit Interface TAG Removal UTOPIA 1 Transmit Interface Cell Generator Cell Receiver Utility Bus Interface EEPROM Interface DPI Receive Interface TAG Adder and MUX RxFIFO UTOPIA 1 Receive Interface Search Tree SRAM Interface 5347drw02
GND DTxDATA[0] DTxDATA[1] DTxDATA[2] DTxDATA[3] DTxFRM VCC GND DTxCLK DRxFRM DRxDATA[0] DRxDATA[1] DRxDATA[2] DRxDATA[3] VCC GND DRxCLK EECS EEDIN EEDOUT EECLK SYS RST SYSCLK GND VCC DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
IDT77V012 PQFP TOP VIEW(3)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
GND CNTRL_B ALE AD[7] AD[6] AD[5] AD[4] AD[3] VCC GND AD[2] AD[1] AD[0] PHYIN T RD WR PH YR ST PH Y C S DATA[31] DATA[30] DATA[29] DATA[28] DATA[27] DATA[26] DATA[25] DATA[24] DATA[23] GND VCC DATA[22] DATA[21] DATA[20] DATA[19] DATA[18] DATA[17] VCC
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Note: 1. All power pins must be connected to a 3.3V 0.3V power supply. 2. All GND pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking.
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IDT77V012
DRxDATA [0] DRxDATA [1] DRxDATA [2] DRxDATA [3] DRxFRM DRxCLK DTxDATA [0] DTxDATA [1] DTxDATA [2] DTxDATA [3] DTxFRM DTxCLK RxDATA [0] RxDATA [1] RxDATA [2] RxDATA [3] RxDATA [4] RxDATA [5] RxDATA [6] RxDATA [7] RSOC RCLAV RENB RxLED RCLK TxDATA [0] TxDATA [1] TxDATA [2] TxDATA [3] TxDATA [4] TxDATA [5] TxDATA [6] TxDATA [7] TSOC
11 12 13 14 10 17 2 3 4 5 6 9 138 137 136 134 133 132 131 130 129 139 141 142 143 122 121 120 119 118 115 114 113 111
O O O O O I/O I I I I I O I I I I I I I I I I O O O O O O O O O O O O
4-bit output data bus used to transfer data to a DPI device [LSB]. 4-bit output data bus used to transfer data to a DPI device [LSB+1]. 4-bit output data bus used to transfer data to a DPI device [LSB+2]. 4-bit output data bus used to transfer data to a DPI device [MSB]. DPI receive start of frame marker. Receive DPI clock. 4-bit input data bus used to transfer data from a DPI device [LSB]. 4-bit input data bus used to transfer data from a DPI device [LSB+1]. 4-bit input data bus used to transfer data from a DPI device [LSB+2]. 4-bit input data bus used to transfer data from a DPI device [MSB]. DPI transmit start of frame marker. Transmit DPI clock. 8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB]. 8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+1]. 8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+2]. 8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+3]. 8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+4]. 8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+5]. 8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [LSB+6]. 8-bit UTOPIA 1 input data bus used to transfer data from a PHY device [MSB]. UTOPIA 1 Receive Start of Cell. UTOPIA 1 Receive Cell Available. UTOPIA 1 Receive Enable. UTOPIA 1 Receive LED, open drain. UTOPIA 1 Receive Clock. 8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB]. 8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+1]. 8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+2]. 8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+3]. 8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+4]. 8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+5]. 8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [LSB+6]. 8-bit UTOPIA 1 output data bus used to transfer data to a PHY device [MSB]. UTOPIA 1 Transmit Start of Cell. Table 1 Pin Description (Part 1 of 4)
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WXSWX2 WXSQ,
HOED7 QRLWSLUFVH' QL3 HOED7 QRLWSLUFVH' QL3 HOED7 QRLWSLUFVH' QL3 HOED7 QRLWSLUFVH' QL3
UHEPX1 QL3 HPD1 QL3
IDT77V012
TCLAV TENB TxLED TCLK TxPRTY EECLK EECS EEDIN EEDOUT AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] PHYCS RD WR ALE PHYRST PHYINT SYSRST SYSCLK CNTRL_A CNTRL_B SCLK ADSP GW CE OE ADDR[0]
128 123 124 125 112 21 18 19 20 96 97 98 101 102 103 104 105 91 94 93 106 92 95 22 23 110 107 58 55 57 62 56 63
I O O O O O O I O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O I I I O O O O O O O O I
UTOPIA 1 Transmit Cell Available. UTOPIA 1 Transmit Enable. UTOPIA 1 Transmit LED, open drain. UTOPIA 1 Transmit Clock. Transmit Parity. EEPROM Clock. EEPROM Chip Select. Serial input from the EEPROM. Serial output to the EEPROM. Utility Bus Address and Data Bus [LSB]. Utility Bus Address and Data Bus [LSB+1]. Utility Bus Address and Data Bus [LSB+2]. Utility Bus Address and Data Bus [LSB+3]. Utility Bus Address and Data Bus [LSB+4]. Utility Bus Address and Data Bus [LSB+5]. Utility Bus Address and Data Bus [LSB+6]. Utility Bus Address and Data Bus [MSB]. Utility Bus PHY Chip Select. Utility Bus Read. Utility Bus Write. Utility Bus Address Latch Enable. PHY Reset, open drain. PHY Interrupt. System Reset. System Clock. Control pin A. Control pin B. SRAM Clock. SRAM Address Status Processor. SRAM Global Write Enable. SRAM Chip Enable. SRAM Output Enable. SRAM Address bus. Tx TAG Size [0]. Number of bytes to remove from cell in transmit direction (LSB). Table 1 Pin Description (Part 2 of 4)
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WXSWX2 WXSQ,
UHEPX1 QL3
HPD1 QL3
IDT77V012
ADDR[1]
64
O I
SRAM Address bus. Tx TAG Size [1]. Number of bytes to remove from cell in transmit direction (LSB+1). SRAM Address bus. Tx TAG Size [2]. Number of bytes to remove from cell in transmit direction (MSB). SRAM Address bus. "Tx TAG Location. Location of TAG in the transmit direction. "0" beginning of cell, "1" end of cell." SRAM Address bus. "Tx Add HEC. Add a HEC placeholder. "0" do not add placeholder, "1" add placeholder." SRAM Address bus. Rx TAG Size [0]. Number of bytes to add to cell in receive direction (LSB). SRAM Address bus. Rx TAG Size [1]. Number of bytes to add to cell in receive direction (LSB + 1). SRAM Address bus. Rx TAG Size [2]. Number of bytes to add to cell in receive direction (MSB). SRAM Address bus. "Rx Rem HEC. Remove HEC from the cell. "0" do not remove the HEC byte, "1" remove the HEC byte." SRAM Address bus. "DPI Mode. Selects DRxCLK direction. "0" switch mode (output), "1" normal mode (input)." SRAM Address bus. "In-StreamTM Direction. Selects the interface that the In-StreamTM cells will be filtered on. "0" transmit DPI interface, "1" receive UTOPIA interface." SRAM Address bus. "Init from EEPROM. Selects whether first four bytes stored in EEPROM are to be written to In-StreamTM Cell Header registers. "0" do not write value to registers, "1" write four byte value from EEPROM to In-StreamTM Cell Header registers." SRAM Address bus. SRAM Address bus. SRAM Address bus. SRAM Address bus. SRAM Address bus. SRAM Address bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. Table 1 Pin Description (Part 3 of 4)
ADDR[2]
65
O I
ADDR[3]
66
O I
ADDR[4]
67
O I
ADDR[5]
68
O I
ADDR[6]
69
O I
ADDR[7]
70
O I
ADDR[8]
54
O I
ADDR[9]
53
O I
ADDR[10]
52
O I
ADDR[11]
51
O I
ADDR[12] ADDR[13] ADDR[14] ADDR[15] ADDR[16] ADDR[17] DATA[0] DATA[1] DATA[2] DATA[3] DATA[4]
50 49 48 47 44 61 26 27 28 29 30
O O O O O O I/O I/O I/O I/O I/O
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QRLWSLUFVH'
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WXSWX2 WXSQ,
UHEPX1 QL3
HPD1 Q L3
IDT77V012
DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] DATA[19] DATA[20] DATA[21] DATA[22] DATA[23] DATA[24] DATA[25] DATA[26] DATA[27] DATA[28] DATA[29] DATA[30] DATA[31] Vcc
31 32 33 34 35 38 39 40 41 42 43 71 74 75 76 77 78 79 82 83 84 85 86 87 88 89 90 7,15,25,37, 46,60,73,80, 100,109,116, 127,135 1,8,16,24,36, 45,59,72,81, 99,108,117, 126,140,144
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power
SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. SRAM Data bus. 3.3V Power supply pins.
GND
Ground
Ground pins.
Table 1 Pin Description (Part 4 of 4)
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WXSWX2 WXSQ,
UHEPX1 QL3
HPD1 Q L3
IDT77V012
VCC VIN VOUT GND IOUT1 IOUT2 IOUT3 IOUT4 TSTG
3.3V Digital Supply Voltage Digital Input Voltage Digital Output Voltage Digital Ground Voltage Output Current CNTRL_A, CNTRL_B Output Current EECLK, EECS, EEDOUT Output Current RxLED, TxLED, PHYRST (open drain) Output Current all outputs except those listed in IOUT1, IOUT2 and IOUT3 Storage Temperature
GND-0.3 GND-0.3 Gv-0.3 0 -- -- -- -- -55
3.6 5.50 VCC 0 12.0 2.0 6.0 6.0 140
V V V V mA mA mA mA C
VCC VIN TA titr titf VIH VIL
Digital Supply Voltage TTL Input Voltage Industrial Operating Temperature Input TTL rise time Input TTL fall time TTL Input High Voltage TTL Input Low Voltage
3.0 GND -40 -- -- 2.0 --
3.6 5.5 +85 2 2 -- 0.8
V V C ns ns V V
|ILI| |ILO| VOH VOL ICC
Input Leakage Current Output Leakage Current TTL Output High Voltage TTL Output Low Voltage Power Supply Current
VCC = 3.3V, VIN = 0V to VCC VOUT = 0V to VCC IOH = -4mA IOL = +4mA 155.52 Mbps
10 10 2.4 -- --
10 10 -- 0.4 80
A A V V mA
CIN COUT CBID
Input Capacitance Output Capacitance Bi-Directional Capacitance
All Inputs All Outputs All Bi-directional Pins
-- -- --
4 6 10
-- -- --
pF pF pF
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WLQ8
WLQ8 WLQ8 WLQ8 [D0
[D0 [D0 [D0 S\7
QL0 QL0 QL0 QL0
VQRLWLGQR& WVH7
VQRLWLGQR& JQLWDUHS2 GHGQHPPRFH5 VQRLWLGQR& JQLWDUHS2 GHGQHPPRFH5 VQRLWLGQR& JQLWDUHS2 GHGQHPPRFH5 VQRLWLGQR& JQLWDUHS2 GHGQHPPRFH5
UHWHPD UD3 UHWHPD UD3
VFLWVLUHWFDUDK& ODFLUWFHO( &' VFLWVLUHWFDUDK& ODFLUWFHO( &' VFLWVLUHWFDUDK& ODFLUWFHO( &' VFLWVLUHWFDUDK& ODFLUWFHO( &'
VJQLWD5 PXPL[D0 HWXORVE$ VJQLWD5 PXPL[D0 HWXORVE$ VJQLWD5 PXPL[D0 HWXORVE$ VJQLWD5 PXPL[D0 HWXORVE$
UHWHPD UD3 UHWHPDUD3
HFQDWLFDSD& HFQDWLFDSD& HFQDWLFDSD& HFQDWLFDSD&
OREP\6
OREP\6 OREP\6 OREP\6
IDT77V012
The 77V012 uses a UTOPIA level 1 interface to receive and transmit ATM cells to and from the PHY device. It has a UTOPIA master interface and operates with a 8-bit data bus. UTOPIA cell level handshake is used to transfer the cells between the ATM layer and the PHY layer. UTOPIA byte level handshake is not supported by the 77V012. The Data Path Interface (DPI) uses a 4-bit data bus, which interfaces the 77V012 to the IDT SwitchStar. The EEPROM holds information for initialization and Discovery/Identify cells. The EEPROM is an option and does not need to be implemented. The Utility Bus interface contains the control pins used to program and read the internal PHY registers. The SRAM interface is used to configure internal registers at reset and to interface with the external SRAM during normal operation. The Misc. interface offers two test pins, that are controlled through registers.
The 77V012 offers a fully compliant UTOPIA Level 1 Receive interface, as specified by the UTOPIA Level 1 specification. The interface is a UTOPIA master that operates with a 8-bit Input Data Bus (RxDATA[7:0]). UTOPIA cell level handshake is used to receive ATM cells from the PHY device. The other signals associated with this interface are Receive Start of Cell (RSOC), Receive Enable (RENB), Receive Cell Available (RCLAV), Receive LED (RxLED), and Receive Clock (RCLK). RCLK is a continuous clock, which is half the frequency of System Clock (SYSCLK). RxLED indicates if there is activity on the UTOPIA receive bus. This open drain signal asserts low when a cell is transferred over the bus, and will stay asserted for 2 RCLK cycles. At 40MHz this is approximately 0.1 seconds.
22
DPI Receive Interface
DRxCLK DRxFRM DRxDATA[3:0]
DTxCLK
DPI Transmit Interface
DTxFRM DTxDATA[3:0]
IDT77V012
EEDIN
Serial EEPROM Interface System Interface
EEDOUT EECS EECLK SYSRS T SYSCLK P HY CS ALE RD WR PHYRST
Utility Bus Interface
P H YI N T AD[7:0]
Figure 2 77V012 Interfaces 8 of 46 March 26, 2001
QRLWDUHS2 HFDIUHWQ, HYLHFH5 $,3278
RCLK RSOC RENB RxDATA[7:0] RCLAV Rx LED TCLK TSOC TENB TxDATA[7:0] TCLAV TxPRTY T x L ED ADDR[17:0] DATA[31:0] SCLK A DS P GW CE OE
HFDIUHWQ, HFLYH' HFDIUHWQ, HFLYH' HFDIUHWQ, HFLYH' HFDIUHWQ, HFLYH'
The 77V012 will assert RENB low upon detection of a high RCLAV. Once RSOC is detected the 77V012 will receive the entire cell without interruption. When a TAG is not being used there is no delay between back to back cells. There is a maximum delay of eight clock cycles between back to back cells when a four byte TAG is being used.
UTOPIA Receive Interface
UTOPIA Transmit Interface
SRAM Interface
CNTRL_A CNTRL_B
Misc. Interface
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IDT77V012
Cells can be dropped on the Rx UTOPIA interface by setting the RxData Cell Filter bit of the Configuration 2 register. This option is to prevent cells from reaching the switch when the 77V012 is in software reset, but the rest of the system is still under normal operation. When this bit is set to a one the 77V012 will drop all data cells and filter only InStreamTM cells, if In-StreamTM filtering is being done on the Rx UTOPIA interface. A hardware reset will clear this bit, while a software reset will not. This register bit must be written to disable the function after a software reset has occurred. When enabled the receive cell counters are disabled, which includes both the UTOPIA Rx Cell Counter registers and the Rx Counters in the Result Node. The transmit section is not affected by this bit. See UTOPIA Receive Register Table for register description. There are no delays between back to back cells when a TAG is not being used, and a maximum eight clock cycle delay between back to back cells when a four byte TAG is being used
Cell (TSOC), Transmit Enable (TENB), Transmit Clock (TCLK), Transmit LED (TxLED), Transmit Parity (TxPRTY) and Transmit Cell Available (TCLAV). TCLK is a continuous clock, which is half the frequency of System Clock (SYSCLK). TxLED indicates if there is activity on the UTOPIA transmit bus. This open drain signal asserts low when a cell is transferred over the bus, and will stay asserted for 2 TCLK cycles. At 40MHz this is approximately 0.1 seconds.
22
TxPRTY is a parity bit for the TxDATA[7:0] bus. Upon detection of a high TCLAV the 77V012 will assert TENB, TSOC and the first valid byte of data. TSOC is one TCLK cycle long and coincides with the first valid byte of data (TxDATA[7:0]). When the entire cell has been transferred the 77V012 will sample TCLAV for cell availability. The PHY will de-assert TCLAV if it cannot accept another cell. When a TAG is not being used there is a maximum of one clock cycle delay between back to back cells. There is a maximum delay of five clock cycles back to back cells when a four byte TAG is being used. There is one register associated with the UTOPIA 1 Transmit interface. Programming the Drop Cell register bit is done with an In-StreamTM programming cell.When this bit is set to a zero the 77V012 will stall the pipeline, if the PHY transmit FIFO is full, thus halting transmission until a high TCLAV is detected. When set to a one the 77V012 will drop cells if the PHY transmit FIFO is full.
The 77V012 offers a fully compliant UTOPIA Level 1 Transmit interface, as specified by the UTOPIA Level 1 specification. The interface is a UTOPIA master that utilizes a 8-bit output data bus (TxDATA[7:0]). UTOPIA cell level handshake is used to transmit ATM cells to the PHY device. Other signals associated with this interface are Transmit Start of
QRLWDUHS2 QRLWDUHS2 QRLWDUHS2 QRLWDUHS2 HFDIUHWQ, WLPVQDU7 $,3278
RCLK (output) RCLAV (input) RENB (output) RSOC (input) RxDATA[7:0] (input)
0
1
2
47
48
49
50
51
52
5347drw05
Figure 3 One Cell Transfer on Receive UTOPIA 1 Bus
RCLK (output) RCLAV (input) R E NB (output) RSOC (input) RxDATA[7:0] (input)
48
49
50
51
52
0
1
47
48
49
50
51
5347drw06
Figure 4 Back-to-Back Cell Transfer without Tag Added 9 of 46 March 26, 2001
IDT77V012
TCLK (output) TCLAV (input) TENB (output) TSOC (output) TxDATA[7:0] (output)
0
1
46
47
48
49
50
51
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Figure 5 One Cell Transfer on Transmit UTOPIA 1 Bus
TCLK (output) TCLAV (input) TENB (output) TSOC (output) TxDATA[7:0] (output)
49
50
51
52
0
1
46
47
48
49
5347drw08
Figure 6 Back-to-Back Cell Transfer without Tag Added
Configuration 2
8002
6
RxData Cell Filter
0-1
0
Allow cells to be dropped on the receive UTOPIA interface. In-StreamTM cells are not affected by the condition of this bit, if they are being filtered on the receive UTOPIA interface. "0" pass cells received on the receive UTOPIA interface, "1" filter and drop data cells on the receive UTOPIA interface.
Table 2 UTOPIA Receive Register Table
Configuration 2
8002
5
Drop Cell
0-1
0
Selects action if PHY transmit FIFO is full: "0" stall pipeline, "1" drop cells.
Table 3 UTOPIA Transmit Register Table
Rx TAG and Mode Select
8006
4
DPI Mode
0-1
Defined by pin
Selects DRxCLK direction. "0" switch mode (output), "1" normal mode (input).
Table 4 DPI Receive Register Table
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HXOD9 WOXDIH'
HXOD9 WOXDIH'
HXOD9 WOXDIH'
HJQD5 HXOD9
HJQD5 HXOD9
HJQD5 HXOD9
HPD1 WL%
HPD1 WL%
HPD1 WL%
WL%
WL%
WL%
VVH UGG$ UHWVLJH5
VVH UGG$ UHWVLJH5
VVH UGG$ UHWVLJH5
HPD1 UHWVLJH5
HPD1 UHWVLJH5
HPD1 UHWVLJH5
IDT77V012
The Data Path Interface (DPI) is a synchronous bus interface designed to transfer ATM cells between two devices. The 77V012 DPI interface supports a 4-bit wide data bus (DPI-4), with separate transmit and receive interfaces. All signals are sampled on the rising edge of their respective clock.
The DPI Transmit Interface is used to transfer cells from the IDT SwitchStar or other DPI device to the 77V012. It has a 4-bit input data bus (DTxDATA[3:0]) and follows the standard DPI timing characteristics as described in the DPI specification. Other signals associated with this interface are DPI Transmit Start of Frame (DTxFRM), and DPI Transmit Clock (DTxCLK). DTxCLK operates at a frequency less than or equal to SYSCLK. DTxCLK can stop if the PHY device signals it cannot accept another cell and the 77V012 has already started to stage the next cell to be transferred in its pipeline. When the PHY signals it can accept additional cells DTxCLK will resume and the cell transfer will continue. DTxFRM is the start of frame marker. This signal is one DTxCLK cycle long and is asserted high one DTxCLK cycle before the first valid nibble of data.
The DPI Receive Interface is used to transfer cells from the 77V012 to the IDT SwitchStar or other DPI device. It has a 4-bit Output Data Bus (DRxDATA[3:0]) and follows the standard DPI timing characteristics as described in the DPI specification. Other signals associated with this interface are DPI Receive Start of Frame (DRxFRM) and DPI Receive Clock (DRxCLK). DRxCLK operates at a frequency less than or equal to SCLK. Depending on the DPI mode selected this clock will be either an input or an output. In Normal Mode DRxCLK is an input to the 77V012. In Switch Mode DRxCLK is a continuous clock generated by the 77V012. There is no flow control in Switch mode, as it is assumed that the IDT SwitchStar will be able to accept all incoming cells (non-blocking). Programming the clock direction is done at reset. DRxFRM is the start of frame marker. This signal is one DRxCLK cycle long and is asserted high one DRxCLK cycle before the first nibble of valid data.
A pull-up or pull-down resistor is connected to ADDR[11:0] signals to select desired register values. The SYSRST signal must be asserted for at least one SYSCLK cycle to load the desired values. On the rising edge of SYSRST the 77V012 will begin loading the register values, which takes an additional 16 SYSCLK cycles. During this 16 clock cycle period all outputs will be tri-stated.
DRxCLK (output) DRxFRM (output) DRxDATA[3:0] (output) 0 1 2 3 103 104 105
5347drw09
Figure 7 One Cell Transfer on Receive DPI Bus
DRxCLK (output) DRxFRM (output) DRxDATA[3:0] (output) 0 1 2 3 103 104 105
5347drw10
Figure 8 Back-to-Back Cell Transfer on Receive DPI Bus
DTxCLK (output) DTxFRM (input) DTxDATA[3:0] (input) 0 1 2 3 103 104 105
5347drw11
Figure 9 One Cell Transfer on Transmit DPI Bus 11 of 46 March 26, 2001
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IDT77V012
DTxCLK (output) DTxFRM (input) DTxDATA[3:0] 104 (input) 105 0 1 2 3 103 104 105
5347drw12
0
Figure 10 Back-to-Back Cell Transfers on Transmit DPI Bus
DTxCLK (output) DTxFRM (input) DTxDATA[3:0] (input) 0 1 103 104 105
5347drw13
Figure 11 DTxCLK Stopping During Cell Transfer
ADDR[2:0] ADDR[3] ADDR[4] ADDR[7:5] ADDR[8] ADDR[9] ADDR[10] ADDR[11]
Tx TAG Size Tx TAG Location Tx Add HEC Rx TAG Size Rx Remove HEC DPI Mode In-StreamTM Direction Init from EEPROM
Number of bytes to remove from the cell in the transmit direction. Valid values are Tx TAG [2:0] from zero to four bytes. "Location of the TAG in the transmit direction. "0" beginning of the cell, "1" end of the cell." Tx TAG [3]
"Add a HEC placeholder to the cell. "0" do not add HEC placeholder, "1" add HEC Tx TAG [4] placeholder." Number of bytes to add to the cell in the receive direction. Valid values are from zero to four bytes. Rx TAG and Mode Select [2:0]
"Remove HEC byte from cell. "0" do not remove HEC byte, "1" remove HEC byte." Rx TAG and Mode Select [3] "Selects direction of DRxCLK. "0" switch mode (output), "1" normal mode (input)." "Interface to filter In-StreamTM programming cells. "0" filter on transmit DPI interface, "1" filter on receive UTOPIA interface." "Write four bytes from EEPROM to In-StreamTM Cell Header registers. "0" do not write four byte value, "1" write four byte value." Table 5 Reset Configuration Pins Rx TAG and Mode Select [4] Rx TAG and Mode Select [5] Rx TAG and Mode Select [6]
Software Reset (In-StreamTM) SYSRST (external pin) PHY reset (register bit) Search Table Reset (register bit)
X X X X X Table 6 Reset Table
12 of 46
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IDT77V012
Resetting the 77V012 can be accomplished with either the external pins or In-StreamTM programming cells, while the PHY and Search Tables are reset with In-StreamTM cells. The System Reset (SYSRST) pin will reset the 77V012 and the PHY devices when asserted low. The 77V012 can also be reset with an InStreamTM cell carrying the Reset command (Message Type ID 0x3), however, this command does not reset the PHY device. When using the SYSRST pin the device will stay in reset for 16 SYSCLK cycles after the rising edge of SYSRST. The PHY can be reset at any time by writing a one to the PHY Reset bit of the Reset register. Writing a one will toggle the external PHYRST pin low for 16 SYSCLK cycles, while the PHY is being reset. This bit will return to zero once the reset command is completed. This method will only reset the PHY device connected to the PHYRST pin. The Search Table is reset by writing a one to the Search Table Reset bit of the Reset register. Writing a one to this register bit will fill the Search Table with Null pointers, which takes 1K to 12K SYSCLK cycles depending on the size of the Search Table. This command only resets the Search Table in the SRAM. Cells can be dropped on the Rx UTOPIA interface by setting the RxData Cell Filter bit of the Configuration 2 register. When this bit is set to a one the 77V012 will drop all data cells and filter only In-StreamTM cells, if In-StreamTM filtering is being done on the Rx UTOPIA interface. A hardware reset will clear this bit, while a software reset will not. This register bit must be written to disable the function after a software reset has occurred. When enabled the receive cell counters are disabled, which includes both the UTOPIA Rx Cell Counter registers and the Rx Counters in the Result Node. The transmit section is not affected by this bit.
The 77V012 can run at a maximum SYSCLK speed of 66MHz. The DPI clocks must run at 40MHz, or greater, to achieve 155.52Mbps data rate with overhead. The Clock Speed vs. Bandwidth Table lists some of the possible data rates and the clock frequencies required to achieve them.
Bit swapping must be performed to convert the 8-bit Tx and Rx of the UTOPIA interface to the 4-bit Tx and Rx of the DPI interface. Cell formatting is big endian, or upper nibble first. The UTOPIA to DPI conversion table illustrates how the 77V012 performs cell formatting.
The Utility Bus interface is used to access the PHY registers. A one to 32-byte read or write command is accomplished by using In-StreamTM cells. Signals associated with the Utility Bus Interface are Chip Select (PHYCS), Address Latch Enable (ALE), Address/Data Bus (AD[7:0]), Read (RD), Write (WR), PHY Reset (PHYRST) and PHY Interrupt (PHYINT). PHYCS is used to validate activity on the Utility Bus. When PHYCS ="0" the Utility Bus is active with valid data transactions. When PHYCS ="1" the Utility Bus is not selected. ALE is an active high signal used to latch the address, on AD[7:0], in the address phase of a Utility Bus read or write operation. AD[7:0] is a byte wide multiplexed bi-directional bus used to read and write data to the PHY.
SYSCLK (MHz)
DTxCLK & DRxCLK (MHz) 40 44 50 66
TCLK & RCLK (MHz) 20 22 25 33
Bandwidth of UTOPIA Interface (cell rate in Mbps) 52 byte cell (w/o HEC) 157 172.7 196.2 259 53 byte cell (normal cell w/HEC) 157 172.7 196.3 259.1 54 byte cell (one byte if TAG added w/HEC) 144 158.4 180 237.6 55 byte cell (two bytes of TAG added w/HEC) 144.3 158.7 180.3 238 56 byte cell (four bytes of TAG added w/o HEC) 140 154 175 231
40 44 50 66
Table 7 Clock Speed vs. Bandwidth Table
bit 7 GFC VPI[3:0] VCI[11:4] VPI[7:4] VCI[15:12]
bit 0
Table 8 UTOPIA to DPI Conversion 13 of 46 March 26, 2001
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bit 3 GFC VPI[7:4] VPI[3:0]
4-IPD
AIPOTU
VQRLWS2 WHVH5 VQRLWS2 WHVH5 VQRLWS2 WHVH5 VQRLWS2 WHVH5
bit 0
IDT77V012
WR is an active low signal used as an enable to write data to an addressed location on the AD[7:0] bus. PHYRST is an active low PHY reset signal. PHYINT is an active low interrupt signal. This signal is driven by the PHY layer and indicates that an interrupt has occurred. The interrupt must be cleared by the controlling CPU before another interrupt event can be reported. Registers associated with the Utility Bus interface are described in the Utility Bus Register Table. The register address range is described in the Address Map.
The EEPROM is an optional device that can be used for initialization and Discovery/Identify cells. The data is broken up into five fields. Bytes [3:0] contain a value that can be read at reset and placed in the InStreamTM Cell Header registers to be used for the In-StreamTM cell header. Bytes [7:4] are not used at this time, while bytes [39:8] contain 32-bytes of data, which is read when a Discovery/Identify command is encountered. Bytes 40 to 127 are reserved and bytes 128 to 255 are user defined. The registers associated with the EEPROM are listed in the EEPROM Register Table. Signals associated with this interface are Clock (EECLK), Chip Select (EECS), Data Out (EEDOUT), Data In (EEDIN), and ADDR[11]. EECLK is generated from SYSCLK and is an output of the 77V012. EECS is an active low chip select signal used to validate a read or write operation. EEDOUT is a serial output data pin to the EEPROM. EEDIN is a serial input data pin from the EEPROM. At reset ADDR[11] selects whether or not to write the first four bytes stored in the EEPROM to the In-StreamTM Cell Header registers. The loading process starts on the rising edge of SYSCLK following the completion of the reset cycle. The loading process takes approximately 2000 SYSCLK cycles to complete, at which time the value is loaded into the registers. The EEPROM can be controlled with the EEPROM register bits, which include Mux Select (EEPROM Mux Sel), Clock Output (EEPROM Clock Out), Chip Select (EEPROM Chip Select), Data Out (EEPROM Out), and Data In (EEPROM In).
A Utility bus read is initiated by an In-StreamTM programming cell. Once the 77V012 interprets the cell as a read command it will drive PHYCS, ALE, RD, and AD[7:0]. The PHY samples the address on the falling edge of ALE. Once PHYCS and RD assert the bus tristates and switches to an input for the PHY to place data on. The PHY drives the bus until the rising edge of PHYCS or RD. One Utility Bus read can include up to 32 bytes of data.
A Utility bus write is initiated by an In-StreamTM programming cell. Once the 77V012 interprets the cell as a write command it will drive PHYCS, ALE, WR, and AD[7:0]. The PHY samples the address on the falling edge of ALE. Once PHYCS and WR assert the 77V012 will write data to the PHY. One Utility Bus write can include up to 32 bytes of data.
PHY Reset
800A
0
PHY Reset
0-1
0
When set high the PHYRST on the Utility Bus Interface will be asserted low for 16 SYSCLK cycles. The register will reset to zero after the command is executed.
Table 9 UTOPIA Receive Register Table
(I) SYSCLK tPALE (O) ALE tALPW
(O)
PHYCS
tPPHY tALR tRDPW
(O)
RD
tAAL
tALA Address Read Data from PHY tDRS tDRH
5347drw14
(I/O) Add/Data[7:0]
Figure 12 Utility Bus Read Operation 14 of 46 March 26, 2001
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RD is an active low signal used as an enable to read data from an addressed location on the AD[7:0] bus.
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IDT77V012
EEPROM Mux Select indicates whether the EEPROM pins will be connected to the In-StreamTM logic, or to the EEPROM registers. When connected to the In-StreamTM logic 32-bytes of data are read from the EEPROM if a Discovery/Identify command is filtered. Controlling the EEPROM from the registers enables the user the flexibility of reading and writing the EEPROM at any time. Programming is accomplished with In-StreamTM cells regardless of the method used to access the EEPROM. EEPROM Clock Out is used to clock the EEPROM when it is being controlled by the registers. This register must be written to twice to execute one EEPROM clock cycle. You must write to the clock register to perform a read or write command. EEPROM Chip Select validates transactions on the EEPROM interface when controlled by the EEPROM registers. EEPROM Out is a 1-bit register used to output data to the EEPROM. EEPROM In is a 1-bit register used to input data from the EEPROM.
cell accounting is being used. Memory sizes can be from 64K x 32-bit to 256K x 32-bit. See the Memory Size Table for valid memory sizes. Signals associated with this interface are Address [17:0] (ADDR[17:0]), Data [31:0] (DATA[31:0]), SRAM Clock (SCLK), Address Status (ADSP), Global Write (GW), Chip Enable (CE) and Output Enable (OE). During normal operation ADDR[17:0] is the address bus used to access the SRAM. Only ADDR[15:0] are required if a 64K x 32-bit SRAM is used. During reset ADDR[11:0] are input pins used to configure TAG parameters, In-StreamTM cell direction, and initialization from EEPROM. DATA[31:0] is a 32-bit bi-directional data bus used to read and write data to the SRAM. SCLK is a synchronous clock output used by the SRAM for all timing references. It is the same frequency as the UTOPIA interface clock. ADSP is a synchronous output used to load the SRAM address registers with a new address. GW is a synchronous global read/write enable. CE is an active low chip enable. OE is an active low output enable. The SRAM address range is described in the Address Map.
The SRAM interface is used to connect the 77V012 to the synchronous flow-through memory. The SRAM contains the Search Tree used to translate the original incoming ATM cell header to the new ATM cell header. The SRAM size is configurable and is dependent on the number of connections desired, the complexity of the Search Tree, and whether
Pin Control
8004
3
EEPROM Mux 0 - 1 Select EEPROM Clock Out 0-1
0
"Indicates if the EEPROM interface will be connected to the internal logic or the EEPROM registers. "0" connected to internal logic, "1" connected to EEPROM registers." "EEPROM clock when EEPROM interface is connected to the EEPROM registers. "0" clock low, "1" clock high." "EEPROM chip select when EEPROM interface is connected to the EEPROM registers. "0" EEPROM interface is selected, "1" EEPROM interface is not selected." EEPROM output bus when EEPROM interface is connected to the EEPROM registers. EEPROM input bus when EEPROM interface is connected to the EEPROM registers.
4 5 6 7
0 0 0 0
EEPROM Chip 0 - 1 Select EEPROM Out 0 - 1 EEPROM In 0-1
Table 10 EEPROM Register Table (Part 1 of 2) 15 of 46 March 26, 2001
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(I) (O) (O) (O)
SYSCLK tPALE ALE PHYCS WR tAAL tALPW
tPPHY tWRPW tAW tALW tALA Address Write Data to PHY
(O) Add/Data[7:0]
tDWS
tDWH
5347drw15
Figure 13 Utility Bus Write Operation
IDT77V012
Rx TAG and 8006 Mode Select
6
Init from EEPROM
0-1
0
"Four byte write from EEPROM to In-StreamTM Cell Header registers at reset. "0" do not write four byte value, "1" write four byte value to registers."
Table 10 EEPROM Register Table (Part 2 of 2)
64K x 32 128K x 32 256K x 32
1.
13K1 16K1 16K1
2.5K2 5K3 5K3
Table 11 Memory Size Table
Best case conditions are limited by the Result Node, which uses a memory block that is 64Kx32-bit in size. 2. This worst case condition is cased by all structures using the same 64Kx32-bit block of memory. 3. Worst case conditions are determined by the number of Search Trees. This worst case condition uses one Search Tree, which resides in a 64Kx32-bit block of memory. Byte 255
Reserved 0x840000 0x83FFFF
User Defined
SRAM (either 64K, 128K, or 256K) 0x800000 0x07FFFF Reserved
128 127
Reserved
77V012 Registers Reserved PHY Registers
40 39
Discovery/Identify cell data
Reserved In-StreamTM cell header
8 7 4 3 0
5347drw16
Figure 15 EEPROM Memory Map
16 of 46
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Figure 14 Address Map
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0x008026 0x008025 0x008000 0x007FFF 0x000100 0x0000FF 0x000000
Aligned on byte boundary (8-bits = 1 byte)
5347drw17
March 26, 2001
IDT77V012
The search of a new header is the combination of a direct lookup table and a search tree, which can be conducted on either 8, 12, 24, 28 or 32-bits of the cell header.
A Leaf Node is a 16-bit address returned from the last level of search. The Leaf Node is combined with the Result Node Offset and Result Bit to form a Result Node Pointer. The Result Node Pointer points to a Result Node that contains either two 32-bit words or four 32-bit words. When the Tunneling bit of the Tunneling Node is equal to one and the VPI Tunneling Enable bit of the Configuration 1 register is set to a one the 18-bit pointer returned from the direct lookup points to a Result Node. The Result Node contains either two or four 32-bit words. When the Tunneling option is enabled the VCI value will not be overwritten. The new header contains the new VPI value, the new GFC value if the Overwrite GFC option is selected, and the new PT/CLP value if the Overwrite PT/CLP option is selected. The Result Node contains the TAG, new cell header and cell accounting information, if enabled. The first 32-bit word of the Result Node contains the TAG, the second 32-bit word contains the new cell header, the third word is the Rx Cell Counter and the fourth word is the Tx Cell Counter. The Rx and Tx Cell Counters are enabled by setting the Cell Accounting On bit in the Configuration 1 register to a one. All tables in the SRAM use programmable offset pointers. There are generally two dedicated areas in the memory, one 4K block for the search table and one 0-64K block for the Result Nodes. The remaining memory is used for the Search Trees. There are several registers associated with the SRAM memory and the searching of a new header. A description for each register is given in the Search Tree Register table.
The first level of search is a direct lookup in the Search Table. The result from this level of search will return the top node of a Search Tree, with up to 4K unique Search Trees in the Search Table. The direct lookup search is conducted on either the first 8 or 12-bits of the VPI field. The Search GFC bit of the Configuration 1 register determines how many bits to use for the direct lookup Search Table. When Search GFC bit equals one the lookup is conducted using the first 12-bits of the header. When the Search GFC bit is set to a zero an 8-bit lookup is implemented, which uses the first 12-bits minus the 4-bit GFC field. The number of bits being used for the direct lookup Search Table determines the amount of memory required for the Search Table. The Search Table is located in memory on 4K x 32-bit block boundaries. When 12-bits are used for the search the table is 4K x 32-bits, when 8bits are being used the size of the Search Table will be 256 x 32-bits. The search offset value, programmed through the Search Table Offset [5:0] of the Table Offset register, is used as the base pointer address. The direct lookup returns an address to a 32-bit memory location [31:0], which contains a 18-bit pointer and a 1-bit indicator. Bits [17:0] are the 18-bit pointer and bit [31] is the Tunneling Bit. The Tunneling bit and the VPI Tunneling Enable bit of the Configuration 1 register indicate what type of node the 18-bit pointer is pointing to, either a Search Table Node or a Tunneling Node. When the result is a Search Table Node, the search is continued by using the next two bits of the header. The two bits are combined with the Root Node, returned from the initial level of search, to traverse the next level of the Search Tree. The result of the two bit search is a 16-bit address that points to either a Non Terminal Node or a Leaf Node. A Non Terminal Node is combined with the next two bits of the header to form a pointer for the next level of search. The two bits are combined with the Root Node of the previous level of search. The result of this two bit search is either another Non Terminal Node or a Leaf Node.
The number of header bits and the type of search determines the number of memory accesses required to complete the search. Refer to the SRAM Memory Access Table for possible lookup combinations and the number of accesses required. The Result Node Tx and Rx cell counters may require additional read and write cycles to the SRAM. When cell accounting is disabled the Tx Counter does not require any additional read or write cycles, while the Rx path requires two read cycles and no write cycles. When cell accounting is enabled the Tx path requires one read and one write cycle, while the Rx path requires three read cycles and one write cycle.
24 28 28 32
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8 12 8 12
1 1 1 1
Table 12 SRAM Memory Access Table
17 of 46
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8 8 10 10
9 9 11
11
March 26, 2001
IDT77V012
12-bit VPI Lookup Search Table (one level of search) 0 1 2 0123 16-bit VCI Search Tree (up to ten levels of search)
4095 0123
0123
TAG
New Header
5347drw18
Figure 16 Lookup Search Table and Search Tree
{SO [5:0]; VPI [11:0]}
18-bit address used for first level of search
Search Table TN
4K or 256 block of memory
31:30 TB
1-bit
18:17 16:15 DC
2-bits
0 TLN
16-bits
SO
TN
TB = 1 64Kx32-bit Memory Block {RNO [1:0]; TLN [15:1];RB [0]} 31 64K 31 TAG New ATM Header 0 RB = 0 RB = 1 64K 64K 0 RNO 00
01
10
Tunneling Node (TN) - 32-bit field returned from the first level of search. Tunneling Bit (TB) - 1-bit field indicating if the search is a VPI tunneling search or a full header lookup. Don't Care (DC) - A 2-bit don't care field. Tunneling Leaf Node (TLN) - 16-bit field returned from the first level of search. This address points to a Result Node. Result Node Offset (RNO) - Offset for memory area used to store the Result Nodes. This register value divides the memory into 64Kx32-bit blocks.
11 64K 256Kx32-bit SRAM Result Bit (RB) - 1-bit field indicating what 32-bit entry RNP is pointing to. RB = 0 points to the TAG and RB=1 points to the new ATM header. Search Offset (SO) - 6-bit offset pointer that points to a 64Kx32-bit memory block and the starting position of the Search Tree.
5347drw19
Figure 17 Header Lookup with VPI Tunneling Enabled, Cell Accounting Disabled
18 of 46
March 26, 2001
IDT77V012
{SO [5:0]; VPI [11:0]} 18-bit address used for first level of search Search Table TN
4K or 256 block of memory
31:30 TB
1-bit
18:17 16:15 DC
2-bits
0 TLN
16-bits
SO
TN
TB = 1 64Kx32-bit Memory Block {RNO [1:0]; TLN [15:2];RB [1:0]} 31 64K RB = 00 01 New ATM Header Rx Counter Tx Counter RB = 01 RB = 10 64K RB = 11 11 64K 256Kx32-bit SRAM 64K 0 RNO 00 31 TAG 0
10
Result Bit (RB) - 2-bit field indicating what 32-bit entry the Result Node pointer is pointing to. RB = 00 points to the TAG, RB=01 points to the new ATM header, RB=10 points to the Rx Counter and RB=11 points to the Tx Counter.
5347drw20
Figure 18 Header Lookup with VPI Tunneling Enabled, Cell Accounting Enabled
Input Header
GFC VPI VCI PT CLP TAG
TAG + New Header VPI VCI
{
{ { { { { {
31
0 31 0
4K Entries (12-bit look-up) 256 Entries (8bit lookup)
31 0
31
0
31
0
{
31 0 TAG New Header Rx Counter Tx Counter
} Accounting
31
0
31 31 0 31
0 31 0
0
5347drw21
Figure 19 Header Lookup
19 of 46
March 26, 2001
IDT77V012
{SO [5:0]; VPI [11:0]}
18-bit address used for first level of search
31
18:17 16:15 STO
2-bits
0 RN
16-bits
STN Search Offset (SO) - 6-bit offset pointer that points to a 64Kx32-bit memory block and the starting position of the Search Tree.
31 64K
0 00 Search Table STN (18-bits) 01 64K
Search Tree Offset (STO) - 2-bit field that points to one of the 64Kx32-bit memory blocks. This 2-bit field is used for all subsequent levels of search. Root Node (RN) - 16-bit field combined with STO to create STN. Search Table Node (STN) - 18-bit field returned from the first level of search. This address points to the top level of a unique Search Tree.
10 64K
11 64K
4K or 256 block of memory
SO
5347drw22
256Kx32-bit SRAM
64Kx32-bit Memory Block
Figure 20 Traversing the Search Tree for a 24-Bit Header
20 of 46
March 26, 2001
IDT77V012
Get next two bits of VCI = [SB0,SB1] and overwrite LSB (bit 0) of RN with SB0 {STO[1:0]; STP[15:1]; SB0[0]}
31
16:15 16-bit address 16-bit address
0 SB0 = 0 SB0 = 1 Search Tree Pointer (STP) - 15-bit address returned from the previous level of search. This is the 16-bit returned address minus the LSB, which was overwritten with SBx. Search Bit (SBx) - Indicates what entry the 16-bit pointer is located in.
16-bit address 16-bit address
SB0 = 0 selects the first 32-bit entry SB0 = 1 selects the second 32-bit entry
Non Terminal Node (NTN) - 16-bit field returned from search. This 16-bit field is combined with STO and SBx to form address for next level of search. Leaf Node (LN) - 16-bit field returned on the last level of search. This field is combined with STO and RB to form an 18-bit address that points to either the TAG, New ATM Header, Tx Counter or Rx Counter.
31 16-bit address SB1 = 1
16:15 16-bit address SB1 = 0
0
SB1 = 0 selects bits [15:0] of 32-bit entry SB1 = 1 selects bits [31:16] of 32-bit entry 15 16-bit address 0 NTN
Get next two bits of VCI = [SB0,SB1] and overwrite LSB (bit 0) of NTN with SB0 {STO[1:0]; NTN[15:1]; SB0[0]}
31
16:15 16-bit address 16-bit address
0 SB0 = 0 SB0 = 1
16-bit address 16-bit address
SB0 = 0 selects bits [15:0] of 32-bit entry SB0 = 1 selects bits [31:16] of 32-bit entry
31 16-bit address SB1 = 1
16:15 16-bit address SB1 = 0
0
SB1 = 0 selects bits [15:0] of 32-bit entry SB1 = 1 selects bits [31:16] of 32-bit entry 15 16-bit address 0 NTN
Subsequent levels of search
15 16-bit address
0 LN
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A 16-bit Leaf Node (LN) is returned on the last level of search. The Leaf Node points to a Result Node (RN).
Figure 21 Traversing the Search Tree (Continued)
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{RNO[1:0]; LN[15:1]; RB[0]} Result Node Pointer
Result Node Pointer (RNP) - 18-bit pointer to a result node. 31 64K 0 00 Result Bit (RB) - 1-bit field indicating what 32-bit entry RNP is pointing to. RB = 0 points to the TAG and RB=1 points to the new ATM header. Result Node Offset (RNO) - Offset for memory area used to store the Result Nodes. This value divides the memory into 64Kx32-bit blocks. 31 TAG 10 64K New ATM Header 11 64K
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01 64K 0
RB = 0 RB = 1
256Kx32-bit SRAM
Figure 22 Result Node without Cell Accounting
{R N O [1 :0 ]; L N [1 5 :2 ]; R B [1 :0 ]} R es u lt N o d e P oin te r R esu lt N od e P o inter (R N P ) - 1 8 - b it p o in te r to a re s u lt n o d e . R esu lt B it (R B ) - 2 -b it f ie ld in d ic a tin g w h a t 3 2 -b it e n try th e R e s u lt N o d e p o in te r is p o in tin g to . R B = 0 0 p o in ts to th e T A G , R B = 0 1 p o in ts to th e n e w A T M h e a d e r, R B = 1 0 p o in ts to th e R x C o u n te r a n d R B = 1 1 p o in ts to th e T x C o u n te r . R esu lt N od e O ffs et (R N O ) - O ffs e t fo r m e m o ry a re a u s e d to sto re th e R e s u lt N o d e s . T h is v a lu e d iv id e s th e m e m o ry in to 6 4 K x 3 2 -b it b lo c k s. 31 TAG 10 64 K N ew ATM H e ade r 11 64 K T x C o u n te r 2 5 6 K x 3 2 -b it S R A M RB = 11 R x C o u n te r 0 RB = 00 RB = 01 RB = 10
31 64 K
0 00
01 6 4K
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Figure 23 Result Node with Cell Accounting
Configuration 1 8001
0
VPI Tunneling Enable
0-1
0
"Enable VPI Tunneling. "0" header translation is done on the full header either 24, 28 or 32-bits, "1" header translation can be done with VPI Tunneling or full header either 8, 12, 24, 28, or 32-bits." "SRAM present, start search engine. "0" there is no SRAM attached, do not start search engine, "1" SRAM is available and configured correctly for operation, start search engine." "Indicates if cell counting on a per VC basis is enabled. Cell counting is done in both the Tx and Rx directions. "0" Cell Counting is disabled (result node is two 32-bit words), "1" Cell Counting is enabled (result node is four 32-bit words)."
1
Translation Enable Cell Accounting On
0-1
0
3
0-1
0
Table 13 Search Tree Register Table (Part 1 of 3)
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4
Null Counting On Search GFC
0-1
0
"Enable Null Cell Counters. "0" Null Cell Counters are disabled, "1" Null Cell Counters are enabled." "Indicates if the GFC field will be included in the search. "0" do not include GFC field in search (Search Table is 256 x 32-bits), "1" include GFC field in search (Search Table is 4K x 32-bits)." "Indicates whether PT/CLP fields will be included in search. "0" do not include PT/ CLP fields in search (eight levels in Search Tree), "1" include PT/CLP fields in search (ten levels in Search Tree)." "Pass or drop Null cells. "0" drop cell when search leads to a null pointer, "1" pass all cell even if they lead to a null pointer." "Insert New Header. "0" do not replace existing header with new header from search, "1" replace existing header with new header found in search." "Overwrite the GFC field with the new header value. "0" do not overwrite GFC field with new value, "1" overwrite GFC field with new value found in search." "Overwrite the PT/CLP fields in the new cell header. "0" do not overwrite the PT/CLP field of the original header with the PT/CLP value found in the search, "1" overwrite the PT/CLP field of the new header with the PT/CLP value found in the search." Offset pointer for Search Table. Divides memory into 4K blocks. Result node offset pointer. Divides memory into 64K blocks. "Writes Null pointers into Search Table. "0" do not write Null pointers into Search Table, "1" write Null pointers into Search Table (will reset back to zero once the operation is completed in approx. 1K to 12K SYSCLK cycles depending on the size of the Search Table). This value is obtained from the Null Pointer Address registers." Null pointer search tree address and value written in search tree. Null pointer search tree address and value written in search tree. Null pointer search tree address and value written in search tree. Header filtered on receive DPI interface. Header filtered on receive DPI interface. Header filtered on receive DPI interface. Header filtered on receive DPI interface. Header filtered on transmit DPI interface. Header filtered on transmit DPI interface. Header filtered on transmit DPI interface. Header filtered on transmit DPI interface.
5
0-1
0
6
Search PT/CLP 0 - 1
0
7 Configuration 2 8002 0 1 2
Pass All Cells Insert New Header
0-1 0-1
0 0 0 0
Overwrite GFC 0 - 1 Overwrite PT/ CLP Search Table Offset Result Node offset Search Table Reset 0-1
Table Offset
8003
5:0 7:6
0x00 0x3F 0x0 - 0x3 0-1
0x00 0x0 0
Reset
800A
1
Null Pointer 800B Address Byte 2 Null Pointer 800C Address Byte 1 Null Pointer 800D Address Byte 0 Rx Null Pointer Header Byte 3 Rx Null Pointer Header Byte 2 Rx Null Pointer Header Byte 1 Rx Null Pointer Header Byte 0 Tx Null Pointer Header Byte 3 Tx Null Pointer Header Byte 2 Tx Null Pointer Header Byte 1 Tx Null Pointer Header Byte 0 8016 8017 8018 8019 801A 801B 801C 801D
1:0
Null Pointer [17:16]
0x0 - 0x3 0x00 0xFF 0x00 0xFF
0x3 0xFF 0xFF NA NA NA NA NA NA NA NA
[7:0] Null Pointer [15:8] [7:0] Null Pointer [7:0]
[7:0] Rx Null Pointer 0x00 Header [31:24] 0xFF [7:0] Rx Null Pointer 0x00 Header [23:16] 0xFF [7:0] Rx Null Pointer 0x00 Header [15:8] 0xFF [7:0] Rx Null Pointer 0x00 Header [7:0] 0xFF [7:0] Tx Null Pointer 0x00 Header [31:24] 0xFF [7:0] Tx Null Pointer 0x00 Header [23:16] 0xFF [7:0] Tx Null Pointer 0x00 Header [15:8] 0xFF [7:0] Tx Null Pointer 0x00 Header [7:0] 0xFF
Table 13 Search Tree Register Table (Part 2 of 3)
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UTOPIA Rx Cell 801E Counter Byte 3 UTOPIA Rx Cell 801F Counter Byte 2 UTOPIA Rx Cell 8020 Counter Byte 1 UTOPIA Rx Cell 8021 Counter Byte 0 UTOPIA Tx Cell 8022 Counter Byte 3 UTOPIA Tx Cell 8023 Counter Byte 2 UTOPIA Tx Cell 8024 Counter Byte 1 UTOPIA Tx Cell 8025 Counter Byte 0
[7:0] Rx Cell 0x00 Counter [31:24] 0xFF [7:0] Rx Cell 0x00 Counter [23:16] 0xFF [7:0] Rx Cell 0x00 Counter [15:8] 0xFF [7:0] Rx Cell Counter [7:0] 0x00 0xFF
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Counter for cells received on receive UTOPIA bus. Counter for cells received on receive UTOPIA bus. Counter for cells received on receive UTOPIA bus. Counter for cells received on receive UTOPIA bus. Counter for cells transmitted on transmit UTOPIA bus. Counter for cells transmitted on transmit UTOPIA bus. Counter for cells transmitted on transmit UTOPIA bus. Counter for cells transmitted on transmit UTOPIA bus.
[7:0] Tx Cell Counter 0x00 [31:24] 0xFF [7:0] Tx Cell Counter 0x00 [23:16] 0xFF [7:0] Tx Cell Counter 0x00 [15:8] 0xFF [7:0] Tx Cell Counter 0x00 [7:0] 0xFF
Table 13 Search Tree Register Table (Part 3 of 3)
Notification Mask
8007
0
PHY Interrupt Mask Rx Null Mask
0-1
0
"Mask Interrupt notification. "0" no Event Notification cell will be generated when a PHY interrupt occurs, "1" generate Event Notification cell when a PHY interrupt occurs." "Mask Interrupt notification. "0" no Event Notification cell will be generated when Rx Null pointer is encountered, "1" generate Event Notification cell when a Rx Null pointer is encountered." "Mask Interrupt notification. "0" no Event Notification cell will be generated when Tx Null pointer is encountered, "1" generate Event Notification cell when a Tx Null pointer is encountered." "Indicates that a PHY interrupt occurred. "0" no PHY interrupts detected, "1" PHY interrupt has been detected on the PHYINT pin." "Indicates that a Rx Null pointer was encountered. "0" no Rx Null pointer has been detected, "1" Rx Null pointer has been detected." "Indicates that a Tx Null pointer was encountered. "0" no Tx Null pointer has been detected, "1" Tx Null pointer has been detected." "Indicates that a PHY interrupt occurred more than 25ms ago, and the Status register has not been serviced. This bit is cleared by writing to the status register. "0" no PHY interrupt detected, "1" PHY interrupt occurred more than 25ms ago and the Status register has not been serviced." "Indicates that a Rx Null pointer was encountered more than 25ms ago, and the Status register has not been serviced. This bit is cleared by writing to the Status register. "0" no Rx Null pointers detected, "1" Rx Null pointer encountered more than 25ms ago and the Status register has not been serviced." "Indicates that a Tx Null pointer was encountered more than 25ms ago, and the Status register has not been serviced. This bit is cleared by writing to the Status register. "0" no Tx Null pointers detected, "1" Tx Null pointer encountered more than 25ms ago and the Status register has not been serviced."
1
0-1
0
2
Tx Null Mask
0-1
0
Status
8008
0
Interrupt Status 0 - 1 Rx Null Pointer 0 - 1 Status
0 0 0 0
2 Timeout Status 8009 0
Tx Null Pointer 0 - 1 Status PHY Interrupt Timer 0-1
1
Rx Null Pointer 0 - 1 Counter
0
2
Tx Null Pointer 0 - 1 Timer
0
Table 14 Interrupt Register Table
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A Null pointer is a unique selectable value that indicates the pointer is not valid and the search should be terminated. The Null pointer points to a Result Node that contains the Tx and Rx Null Cell Counters. The Tx and Rx Null Cell Counters are enabled by setting the Null Counting On bit of the Configuration 1 register. The Null cell counters can be enabled without enabling the Tx and Rx Cell Counters. When a Null cell is encountered the cell is either dropped or passed, depending on bit 7 of the Configuration 1 register. When the drop option is enabled the search is cancelled and the header of the violating cell is placed in either the Tx or Rx Null Pointer Header registers and the appropriate Null counter is incremented, if enabled. An Event Notification cell will be generated if the appropriate mask bit is set in the Notification Mask register. The appropriate Null Pointer Status bit of the Status register will be updated regardless of the condition of the Notification Mask register bits. See the Search Tree Register Table for a description of the Tx and Rx Null Pointer registers.
mine if the interrupt is cleared. The 77V012 will generate a Event Notification cell, appropriate mask bit must be set to a one, if the interrupt is not cleared within 25ms of when the interrupt occurred and will set the appropriate Timeout Status bit. It will generate additional Event Notification cells on 12ms intervals, thereafter, until the interrupt is cleared. It is the CPU's responsibility to clear the interrupt and/or notify higher layers that an interrupt has been encountered. Interrupts are cleared by the CPU writing to the Status register. Writing a one will clear the interrupt and reset the register back to zero. See Interrupt Register Table for description of interrupt registers.
The Tx and Rx Cell Counters are enabled by writing a one to the Cell Accounting On bit in the Configuration 1 register. When enabled (set to a one) the Result Node becomes four entries deep, with the third entry being the Rx Cell Counter and the fourth entry being the Tx Cell Counter. Each counter is 32-bits and is implemented as a wrap around counter. These are per VC counters. A global cell count is stored in the UTOPIA Tx and Rx Cell Counter registers. These counters are always enabled and will increment each time a cell is transmitted or received over the UTOPIA interface. They can be read at any time, and will roll over once the maximum cell count is reached. The counters are reset by writing zeros to the register. See Search Tree Register Table for register description. The Result Node and Global Rx cell counters are disabled if the RxData Cell Filter bit of the Configuration 2 register is set to a one. This also includes the counting of In-StreamTM cells. The Tx cell counters are not affected by this register bit.
When an interrupt occurs the Status register will indicate were the interrupt occurred. The PHY Interrupt, Rx Null and Tx Null Mask bits of the Notification Mask register determine if an Event Notification cell will be generated when an interrupt is encountered. The 77V012 will not generate an Event Notification cell when an interrupt occurs if the bits are set to the default zero, and will generate a Event Notification cell if set to a one. The Timeout Status register is a read only register that indicates an interrupt occurred more than 25ms ago. It is used to verify that the interrupts are being serviced by the CPU. Once the interrupt is detected the 77V012 will monitor the appropriate bit of the Status register to deter-
Configuration 2 8002 Pin Control Rx TAG and Mode Select 8004 8006
3 0
Rx Move PT/CLP
0-1
0 0
"Move the PT/CLP fields from the original header into the 4-byte TAG area. "0" do not move the PT/CLP fields, "1" move PT/CLP fields." "Enables writing to pin configurable registers. "0" pin configurable registers are read only, "1" pin configurable registers are read/write."
Override Pin Control 0 - 1
[2:0] Rx Tag Size [2:0] 3 Rx Remove HEC
0x0 - 0x4 Defined by pin Number of bytes to add to the received cell. 0-1 0x00 0xFF 0x00 0xFF 0x00 0xFF Defined by pin "Remove HEC from cell. "0" do not remove HEC byte from cell, "1" remove HEC byte from cell." 0x00 0x00 0x01 TAG added to In-StreamTM programming cells. TAG added to In-StreamTM programming cells. TAG added to In-StreamTM programming cells.
In-StreamTM TAG Byte 3 In-StreamTM TAG Byte 2 In-StreamTM TAG Byte 1
8012 8013 8014
[7:0] In-StreamTM TAG [31:24] [7:0] In-StreamTM TAG [23:16] [7:0] In-StreamTM TAG [15:8]
Table 15 Interrupt Register Table
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VWSXUUHWQ, JQLUDHO& GQD JQLWHUSUHWQ, VWSXUUHWQ, JQLUDHO& GQD JQLWHUSUHWQ, VWSXUUHWQ, JQLUDHO& GQD JQLWHUSUHWQ, VWSXUUHWQ, JQLUDHO& GQD JQLWHUSUHWQ,
emaN tiB
# sserddA emaN tiB retsigeR retsigeR
VUHWQLR3 OOX1 VUHWQLR3 OOX1 VUHWQLR3 OOX1 VUHWQLR3 OOX1
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IDT77V012
In-StreamTM TAG Byte 0
8015
[7:0] In-StreamTM TAG [7:0]
0x00 0xFF
0xF0
TAG added to In-StreamTM programming cells.
Table 15 Interrupt Register Table
SRAM IDT71V633 ADSL PHY SWITCHStAR IDT77V400 & IDT77V500
OC-3
ATM PHY
Header Xlater IDT77V012
DPI to UTOPIA 2 IDT77V011
UTOPIA 1
4-bit DPI
4-bit DPI
UTOPIA 2
Header
Payload Header Header Payload TAG
Header Payload TAG
Figure 24 Transmit Tag Routing Diagram
Configuration 2 8002 Pin Control Tx TAG 8004 8005
4 0
Tx Move PT/CLP 0 - 1 Override Pin Control 0-1
0 0
"Move the PT/CLP field from the 4-byte TAG area to the cell header. "0" do not move PT/CLP fields, "1" move PT/CLP fields." "Enables writing to pin configurable registers. "0" pin configurable registers are read only, "1" pin configurable registers are read/write."
[2:0] Tx Tag Size [2:0] 0 - 4 3 4 Tx Tag Location Tx Add HEC 0-1 0-1
Defined by pin Number of bytes to remove from the ATM cell. Defined by pin "TAG location in Tx direction. "0" TAG is located at beginning of cell, "1" TAG is located at end of cell." Defined by pin "Add a HEC place holder in the Tx direction. "0" do not add a HEC place holder, "1" add a HEC place holder." Table 16 Interrupt Register Table
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IDT77V012
SRAM IDT71V633 ADSL PHY SWITCHStAR IDT77V400 & IDT77V500
OC-3
ATM PHY
Header Xlater IDT77V012
DPI to UTOPIA 2 IDT77V011
ADSL PHY
ADSL PHY UTOPIA 1 4-bit DPI 4-bit DPI UTOPIA 2
Header
Payload TAG TAG New Header Payload
New Header New Header
Payload
Payload
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Figure 25 Receive Tag Routing Diagram
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A TAG can be added to the cell in the Rx direction and removed in the Tx direction. It is added to the beginning of the cell and can be up to four bytes long. Programming the size of the TAG for both the Tx and Rx direction is done with external pins and internal registers, with each direction being individually programmed. The registers associated with the TAG are listed in the Rx and Tx TAG Register Tables.
ADDR[3] specifies if the TAG is located at the beginning or end of the cell. When ADDR[3] ="0" the TAG is located at the beginning of the cell, and when ADDR[3] ="1" the TAG is located at the end of the cell. This value is stored in the Tx TAG Location bit of the Tx TAG register. ADDR[4] specifies if a HEC placeholder is to be added to the cell. When ADDR[4] = "0" a placeholder is not added, and if ADDR[4] = "1" a placeholder is added to the cell. This value is stored in the Tx Add HEC bit in the Tx TAG register.
A TAG is added in the Rx direction by first configuring the external pins and then configuring the internal registers. The external pins are multiplexed with the SRAM address pins and are configured at reset. ADDR[7:5] is a 3-bit field that sets the receive TAG size. This TAG can be from zero to four bytes in size. The lower order bytes, in the Result Node, are used when the TAG size is less than four bytes. Therefore, a one byte TAG is appended to bits zero through seven of the possible 32-bits in the TAG field. The value of ADDR[7:5] is stored in the Rx TAG Size [2:0] bits of the Rx TAG and Mode Select register. The header of the in coming cell will be appended to the TAG area when the search engine is not enabled and four bytes of TAG are to be added. When less than four bytes of TAG are added the most significant bytes are appended. ADDR[8] determines if the HEC byte should be removed or not. Setting ADDR[8] low will leave the HEC byte intact, while setting ADDR[8] high removes the HEC byte, thus reducing the number of bytes in the cell by one. The value of ADDR[8] is stored in the Rx Remove HEC bit of the Rx TAG and Mode Select register. The In-StreamTM 1,2,3 and 4 registers indicate the value of the TAG to be added to In-StreamTM programming cells. This value will only be used for In-StreamTM cells. The default value is 0x000001FX, which can be changed by writing to registers with In-StreamTM cells. The Move PT/CLP bit of the Configuration 2 register will move the PT and CLP fields of the new header value into the TAG area if set high and will leave the original value intact if set low. Moving these fields, when switching on the TAG area, enables a DPI device or SwitchStar to find OAM cells, do low priority cell discards and EFCI processing. This option is only valid if using all four bytes of TAG and switching is being done on the TAG.
In-StreamTM programming cells are used to carry commands to the 77V012 and for the CPU to receive information from the 77V012. Cells are received on either the DTxDATA[3:0] bus or the RxDATA[7:0] bus, depending on the condition of Instream Direction bit of the Rx TAG and Mode Select register, which can be configured after reset. All cells received on the selected data bus are filtered by the cell interpreter to determine if they are In-StreamTM programming cells. In order to be recognized, In-StreamTM programming cells have a unique cell header. The default value is 0x000001FX, which can be changed by writing to the In-StreamTM Cell Header 1, 2, 3 and 4 registers. All four registers can be written to in one four byte write with an In-StreamTM cell. The bytes are written MSB to LSB. The new cell header will be used for returning a Reply Notification cell, following the write operation. The 77V012 supports the following set of In-StreamTM functions, Discover/Identify, Reset, Register Read, Register Write, Event Notification and Reply Notification. The Discover/Identify command is sent by the CPU to the 77V012, and is used to either discover the 77V012 or to ensure that the 77V012 is still attached (heart beat). The Reset command is sent from the CPU to the 77V012, which indicates that the 77V012 must perform a hard reset and re-initialize itself to its default state. The Register Read command is used to read the value of one or more registers. Up to 32-bytes can be read with one In-StreamTM cell. The Register Write command is used to write a value to one or more registers. Up to 32-bytes can be written with one In-StreamTM cell. The Event Notification command is sent from the 77V012 to the CPU and indicates that an event has happened that requires CPU intervention. The Reply Notification command is sent from the 77V012 to the CPU in response to command cells sent by the CPU. The 77V012 will generate a Reply Notification response to a Discover/Identify, Register Read and Register Write command, but not for a Reset command. This option is enabled by setting the Acknowledge Request bit in the Message Type Field of the In-StreamTM command cell. The In-StreamTM cell format is broken up into six sections, which vary slightly depending on the type of command the cell caries.
A TAG is removed in the Tx direction by configuring the external pins, which are multiplexed with the SRAM address pins ADDR[4:0]. ADDR[2:0] is a 3-bit field that sets the Tx TAG size. Valid TAG sizes are from zero to four bytes. This value is stored in the Tx TAG Size bits of the Tx TAG register.
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JQLPPDUJRU3 PDHUW6Q, JQLPPDUJRU3 PDHUW6Q, JQLPPDUJRU3 PDHUW6Q, JQLPPDUJRU3 PDHUW6Q,
HFDIUHWQ, JD7 HFDIUHWQ, JD7 HFDIUHWQ, JD7 HFDIUHWQ, JD7 JD7 WLPVQDU7 JD7 WLPVQDU7 JD7 WLPVQDU7 JD7 WLPVQDU7 JD7 HYLHFH5 JD7 HYLHFH5 JD7 HYLHFH5 JD7 HYLHFH5
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IDT77V012
The first five bytes contain the cell header. The In-StreamTM programming cell address is in the first 28-bits with the default value of GFC =0x0, VPI =0x0, VCI =0x001F, PT/CLP =0xX, where X=don't care. The remaining byte is the HEC. Bytes six and seven of the cell contain the Transaction ID information. This field is two bytes wide and is used to correlate messages requiring a reply to a command. This allows more than one command to be sent to a device without waiting for a Reply Notification cell, as the field is copied from the Command cell to the Reply Notification cell. The 2-byte field is set to zero when an Event Notification cell is generated by the 77V012, with the zero value being valid for this condition only. It is up to the CPU to generate and manage values for it's In-StreamTM commands and not re-use the value for some set amount of time. Byte 8 contains the Message Type field, which indicates what type of command the cell contains. Bit location eight is not used. Bit seven is the Acknowledge Request bit, which indicates if an acknowledgement to the Command cell is required or not. When a Reply Notification cell has to be returned this bit is set to a one. When the Reply Notification cell is returned the bit is reset to zero by the 77V012. This option is not valid with the Reset command, which does not return a Reply Notification cell. Bit six is the Acknowledge bit which indicates whether the cell is a Reply Notification cell or a Command cell. This bit is set to a zero when the cell is a Command cell, and is set to a one, by the 77V012, when the cell is a Reply Notification cell. Bits one through five are the Message Type Indicator. There are currently five commands for this field. The Discover/ Identify (value = 0x2) command, which will generate a Reply Notification cell with 32 bytes of device specific data located in the Message Data field. The Reset (value = 0x3) command performs a reset on the 77V012. There is no Reply Notification cell returned for this command. The Read Registers (value = 0x5) command performs a read operation to a set of consecutive registers. One to 31 bytes can be read with one In-StreamTM cell starting at the specified base address when accessing the 77V012 internal registers, while up to 32-bytes can be accessed with one In-StreamTM cell when reading from the SRAM. The returned register data is contained in the Message Data field. The Write Registers (value = 0x6) command performs a write operation to a set of consecutive registers. One to 31 bytes can be written with one In-StreamTM cell starting at the specified base address when accessing the 77V012 internal registers, while up to 32-bytes can be accessed with one InStreamTM cell when writing to the SRAM.The data to be written is contained in the Message Data field. The Event Notification (value = 0x8) command generates a Event Notification cell indicating that an interrupt has been detected. Bytes 9 through 15 are the Device ID field. There are two formats to this field depending on the type of command the cell carries. When the cell contains either the Register Read/Write, or Event Notification command this field must contain a value of 0x01 in byte location 9 to be valid. The remaining six bytes are not used and should contain zeros. When the cell contains the Discovery/Identify command this field contains data from the EEPROM, with data from EEPROM byte location 8 being written to the first byte position of this field.
Bytes 16 through 51 are the Message Data field. The layout of this field is dependant on the Message Type field. A Read or Write command will have a Message Data field divided into three sub fields. The first sub field is one byte wide and indicates how many bytes of data are valid in the data portion of the Message Data field. The second sub field is three bytes wide and contains the base address for the Read or Write command. The third sub field is the valid data and padding. Valid data is written starting at the base address in accordance with the number of valid bytes indicator (first sub field). The remaining space, if any, is padded with zeros. A Discover/Identify command has a Message Data field divided into two sub fields.The first sub field is the first 25-bytes of the Message Data field, which contains up to 25 bytes read from the EEPROM, starting at EEPROM byte location 15. The remaining bytes are reserved. An Event Notification command will have a Message Data field split into two sub fields. The first sub field is two bytes wide and contains an event number, which is always 0x0100. The second sub field contains one byte of data (byte 18) indicating what type of event happened, which is described in the Event Notification Table. The remaining bytes 19 to 51 are padding and contain zeros. Bytes 52 and 53 contain the CRC-10 trailer, with the upper six bits of byte 52 containing zeros. The CRC-10 is generated and used in the same manner as in AAL3/4 cells.
The are two types of Notification cells, Event and Reply, that can be generated by the 77V012. The 77V012 will generate an Event Notification Cell under three different conditions, if the appropriate mask bit(s) are set to a one. The first condition occurs when an interrupt is detected on the external PHYINT pin. The second condition is if a Rx Null Pointer is found in the search, and the third is when a Tx Null Pointer is found in the search. It is up to the CPU to clear the interrupt, or notify higher layers that an interrupt has occurred. A second Event Notification cell will be generated if the interrupt is not cleared in 25ms. Additional Event Notification cells will be generated every 12ms thereafter until the interrupt is serviced. A new event will not be reported until the related interrupt register bit has been cleared. The 77V012 will generate a Reply Notification cell, if the Acknowledge Request bit is set to a one. The Reply Notification cells enable the CPU to keep status of its command cells.
The 77V012 offers two external control pins, CNTRL_A and CNTRL_B, that can be connected to external devices for system design engineer usage. Both of these signals are low after reset. There is also a register bit associated with each signal, which is described in the Misc. Register table.
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VOOH& QRLWDFLILWR1 VOOH& QRLWDFLILWR1 VOOH& QRLWDFLILWR1 VOOH& QRLWDFLILWR1 VHUXWDH) FVL0 VHUXWDH) FVL0 VHUXWDH) FVL0 VHUXWDH) FVL0
March 26, 2001
IDT77V012
Rx TAG and Mode Select
8006
5
In-StreamTM Direction
0-1
Defined by pin "Indicates what interface the In-stream cells will be filtered on. "0" input on the ADDR[10] transmit DPI interface and output on the receive DPI interface, "1" input on the receive UTOPIA interface and output on the transmit UTOPIA interface." 0x00 0x00 0x01 0xF0 Cell header for In-StreamTM programming cells. Cell header for In-StreamTM programming cells. Cell header for In-StreamTM programming cells. Cell header for In-StreamTM programming cells.
In-StreamTM Cell 800E Header Byte 0 In-StreamTM Cell 800F Header Byte 1 In-StreamTM Cell 8010 Header Byte 2 In-StreamTM Cell 8011 Header Byte 3
[7:0] In-StreamTM Header [31:24] [7:0] In-StreamTM Header [23:16] [7:0] In-StreamTM Header [15:8] [7:0] In-StreamTM Header [7:0]
0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF
Table 17 In-StreamTM Register Table
byte 1 ATM Header byte 5 byte 6 byte 7 byte 8 byte 9 Device ID byte 15 byte 16
Transaction ID Message Type
Message Data and/or Padding
byte 51 byte 52 Trailer byte 53
5347drw28
Figure 26 General Format In-Stream TM Programming Cell
UNI Cell Header (five byte field) Bit 8 7 GFC VPI VCI VCI HEC PT CLP 6 5 4 3 VPI VCI 2 1 1 2 VPI 8 7 6 5 VPI VCI VCI VCI HEC PT CLP NNI Cell Header (five byte field) Bit 4 3 2 1 1 2 3 4 5
5347drw30
Byte
3 4 5
5347drw29
Figure 27 Valid Header Formats for In-Stream TM Programming Cell
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March 26, 2001
Byte
QRLWSLUFVH'
HXOD9 HJQD5 VVHUGG$ WOXDIH' HXOD9 HPD1 WL% WL% UHWVLJH5
HPD1 UHWVLJH5
IDT77V012
Command Cell Transaction ID (two byte field) Bit 8 7 6 5 4 3 2 1
Notification Cell Transaction ID (two byte field) Bit 8 7
0 0
6
0 0
5
0 0
4
0 0
3
0 0
2
0 0
1
Byte
Copied from Command Cell
7
0
0
7
5347drw31
Figure 28 Valid Transaction Field Formats for In-StreamTM Programming Cell
Message Type (one byte field) Bit 8 7 6 5 4 3 2 1 8
Message Type ID Acknowledge Bit Acknowledge Request Bit Not Used
5347drw32
TM
Figure 29 Valid Message Type Field Format for In-Stream
Programming Cell
Discovery/Identify Command Cell Device ID (seven byte field) Bit 8 7 6 5 4 3 2 1 9 10 11 12 13 14 Data from EEPROM 15
5347drw33a
Read/Write/Event Notification Command Cell Device ID (seven byte field) Bit 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 1 9 10 11 12 13 14 15
5347drw33
Data from EEPROM
Not Used Not Used
Byte
Byte Byte
Copied from Command Cell
6
0
0
6
Byte
Not Used Not Used Not Used Not Used
Figure 30 Valid Device ID Field Format for In-StreamTM Programming Cell
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March 26, 2001
IDT77V012
Read/Write Command Cell Message Data and/or Padding Field (36 byte field) Bit 8 7 6 5 4 3 2 1 16 17 18 8 7 6 5 Event Notification Cell Message Data and/or Padding Field (36 byte field) Bit 4 3 2 1 16 17 18
Number of valid bytes Base address Base address Base address Data and/or padding
Event number Event number Data and/or padding
Byte
19 20
Data and/or padding
51
5347drw34
Data and/or padding
51
5347drw35
Discover/Identify Command Cell Message Data and/or Paddind Field (36 byte field) Bit 8 7 6 5 4 3 2 1 16
Data from EEPROM
Reserved
41
Reserved
51
5347drw36
Figure 31 Valid Message and/or Data Field Formats for In-StreamTM Programming Cell
Trailer (two byte field) Bit 8
0
7
0
6
0
5
0
4
0
3
0
2
1
CRC10
53
5347drw37
Figure 32 Valid Trailer Field Format for In-Stream TM Programming Cell
Discover/ Identify Reset Read Registers Write Registers Event Notification
2 3
This command will generate an Reply Notification cell containing 32 bytes of device specific data, which is stored in bytes 8 through 40 of the EEPROM. Performs a reset on 77V012 device. No Reply Notification cell is returned acknowledging that the reset command has been completed. Read from a consecutive number of registers. Write to a consecutive number of registers. An unsolicited Event Notification cell indicating an event has taken place. The event can be either a PHY interrupt, a Rx Null pointer, or a Tx Null pointer. Table 18 In-Stream TM Programming Message Type Indicator
5 6 8
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Byte
CRC10
52
QRLWSLUFVH'
Byte
Data from EEPROM
40
March 26, 2001
Byte
', HS\7 HJDVVH0
HPD1
IDT77V012
7:6 5 4 3 2 1 0
Not Used
Tx Null Pointer Error Tx Time Out Rx Null Pointer Error Rx Time Out PHY Interrupt Status PHY Time Out
A Null pointer has been detected in the transmit direction. A Null pointer has been detected in the transmit direction, but the Status register has not been cleared. A Null pointer has been detected in the receive direction. A Null pointer has been detected in the receive direction, but the Status register has not been cleared. A PHY interrupt has been detected. A PHY interrupt has been detected, but the Status register has not been cleared. Table 19 Event Notification Table
Pin Control
8004
1
Control A
0-1
0
"Stores condition of Control A pin. "0" CTRL_A = "0", "1" CTRL_A = "1"." "Stores condition of Control B pin. "0" CTRL_B = "0", "1" CTRL_B = "1"."
2
Control B
0-1
0
Table 20 Misc. Register Table
(industrial: Vcc = 3.3V + 10%, TA = -40oC to 85oC)
tCYC tCH tCL
SYSCLK Cycle Time SYSCLK High Time SYSCLK Low Time UTOPIA TCLK/RCLK Cycle Time UTOPIA TCLK/RCLK High Time UTOPIA TCLK/RCLK Low Time
15 6 6 30 13 13 1 8 1 1 8 1 15 6 6 6 2 --
-- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tUCYC tUCH tUCL tTOV tUTS tUTH tROV tURS tURH tDCYC tDCH tDCL tDTS tDTH tPDRD tALPW tALR tALW tRDPW
TxDATA, TENB, TSOC, TxPRTY, TxLED Output Valid from TCLK TCLAV to TCLK Setup Time TCLAV to TCLK Hold Time RENB, RxLED Output Valid from RCLK RxDATA, RSOC, RCLAV to RCLK Setup Time RxDATA, RSOC, RCLAV to RCLK Hold Time DPI DTxCLK/DRxCLK Cycle Time DPI DTxCLK/DRxCLK High Time DPI DTxCLK/DRxCLK Low Time DTxFRM, DTxDATA to DTCLK Setup Time DTxFRM, DTxDATA to DTCLK Hold Time DRxCLK to DRxDATA(0-3), DRxFRM Propagation Delay ALE Pulse Width SYSCLK to RD Low Propagation Delay SYSCLK to WR Low Propagation Delay RD Pulse Width
20 -- -- 20 -- -- -- -- -- -- -- 8 -- 20 20 --
30 -- -- 60
ns ns ns
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March 26, 2001
WLQ8
[D0
QRLWSLUFVH'
QL0
QRLWSLUFVH' UHWHPDUD3
HXOD9 HJQD5 VVHUGG$ WOXDIH' HXOD9 HPD1 WL% WL% UHWVLJH5
VFLWVLUHWFDUDK& ODFLUWFHO( &$ VFLWVLUHWFDUDK& ODFLUWFHO( &$ VFLWVLUHWFDUDK& ODFLUWFHO( &$ VFLWVLUHWFDUDK& ODFLUWFHO( &$
WQHY(
UHEPX1 WL% OREP\6
HPD1 UHWVLJH5
IDT77V012
tAAL
Address to ALE Falling Edge Setup Time Address to ALE Falling Edge Hold Time Data to rising edge of RD Setup Time Data to rising edge of RD Hold Time Data to rising edge of WR Setup Time Data to rising edge of WR Hold Time WR Pulse Width SYSCLK to PHYINT Setup Time SYSCLK to PHYINT Hold Time ALE falling edge to WR falling edge ALE to SYSCLK Propagation Delay SYSCLK to PHYCS Propagation Delay SYSCLK to PHYRST Propagation Delay SYSCLK to RCLK Propagation Delay SYSCLK to TCLK Propagation Delay SYSCLK to DRxCLK Propagation Delay SYSCLK to DTxCLK Propagation Delay SYSCLK to CONT_A Propagation delay SYSCLK to CONT_B Propagation delay SYSRST Pulse Width SCLK Cycle Time SCLK High Time SCLK Low Time
20 10 5 1 5 1
-- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tALA tDRS tDRH tDWS tDWH tWRPW tPINTS tPINTH tAW tPALE tPPHY tPPHYR tPRCLK tPTCLK tPDRxCLK tPDTxCLK tPCNTA tPCNTB tRSTW tsCYC tsCH tsCL tPADSP tPOE tPADD tPDAT tSD tHD tECYC tPECLK tSEDI tHEDI
30 10 2 30 -- -- -- -- -- -- -- -- -- 100 30 13 13 -- -- -- -- 10 2 1000 -- -- 2
20 20 20 15 13 10 10 20 20 -- -- -- -- 20 9 20 25 -- -- -- 20 10 --
SCLK to SRAM ADSP Propagation Delay SCLK to SRAM OE Propagation Delay SCLK to SRAM Address Propagation Delay SCLK to SRAM Dataout Propagation Delay SCLK to SRAM Data In Setup Time SCLK to SRAM Data In Hold Time EECLK Cycle Time SYSCLK to EECLK, EECS, EEDOUT Propagation Delay SYSCLK to EEDIN Setup Time SYSCLK to EEDIN Hold Time
ns ns ns ns ns ns ns ns ns ns
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March 26, 2001
WLQ8
[D0
QL0
UHWHPDUD3
OREP\6
IDT77V012
tCYC SYSCLK tCH tCL
5347drw38
Figure 33 System Clock Timing Waveform
SYSCLK tPRCLK RCLK
5347drw39
Figure 34 System Clock to UTOPIA Receive Clock Propagation Delay
SYSCLK tPTCLK TCLK
5347drw40
Figure 35 System Clock to UTOPIA Transmit Clock Propagation Delay
SYSCLK tPDRxCLK DRxCLK Figure 36 System Clock to DPI Receive Clock Propagation Delay
5347drw41
SYSCLK tPDTxCLK DTxCLK Figure 37 System Clock to DPI Transmit Clock Propagation Delay
5347drw42
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March 26, 2001
IDT77V012 tUCYC TCLK tUCH tTOV TxDATA(0-7), TENB, TSOC, TxLED, TxPRTY tUTS TCLAV Figure 38 UTOPIA Transmit Timing Waveform tUTH
5347drw43
tUCL
RCLK
tROV RENB, RxLED
tURS
tURH
RxDATA(0-7), RSOC, RCLAV
Figure 39 UTOPIA Receive Timing Waveform tDCYC DTxCLK tDCH tDCL tDTS DTxFRM, DTxDATA(0-3) tDTH
5347drw44
5347drw45
Figure 40 DPI Transmit Timing Waveform
DRxCLK
tPDRD DRxFRM, DRxDATA(0-3)
5347drw46
Figure 41 DPI Receive Timing Waveform
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March 26, 2001
IDT77V012
SYSCLK
tPPHYR
PHYRST
5347drw47
Figure 42 System Clock to PHYRST Propagation Delay
SYSCLK
tPINTS tPINTH
PH YINT
5347drw48
Figure 43 System Clock to PHYINT Propagation Delay
tRSTW
SYSRST
5347drw49
Figure 44 SYSRST Timing Waveform
tPECLK SYSCLK EECS EECLK EEDO tSEDI EEDI
5347drw50
tHEDI
Figure 45 Timing Waveform for EEPROM Read and Write Cycles
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March 26, 2001
IDT77V012
Figure 46 Timing Waveform for SRAM Read and Write Cycles
Device ID
8000
7-0 0
Device Version NA Number VPI Tunneling Enable Translation Enable Not Used Cell Accounting 0 On Null Counting On Search GFC 0 0 0
Device version number. 77V012 Rev A = 0x10, 77V012 Rev B = 0x11. "Enable VPI tunneling. "0" header translation is done on the full header either 24, 28, 32-bits, "1" header translation can be done with VPI Tunneling or full header either 8, 12, 24, 28 or 32-bits." "SRAM present, start search engine. "0" there is no SRAM attached, do not start search engine, "1" SRAM is available and configured correctly for operation, start search engine."
Configuration 1 8001
1
0
2 3
"Indicates if cell counting on a per VC basis is enabled. Cell counting is done in both the transmit and receive directions. "0" cell counting is disabled (result node is two 32bit words), "1" cell counting is enabled (result node is four 32-bit words)." "Enable Null cell counters. "0" Null cell counters are disabled, "1" Null cell counters are enabled." "Indicates if the GFC field will be included in the search. "0" do not include GFC field in search (Search Table is 256 x 32-bits), "1" include GFC field in search (Search Table is 4K x 32-bits)." "Indicates whether PT/CLP fields will be included in the search. "0" do not include PT/ CLP fields in search (eight levels in Search Tree), "1" include PT/CLP fields in search (ten levels in Search Tree)." "Pass or drop Null cells. "0" drop cell when search leads to a null pointer, "1" pass all cells even if they lead to a null pointer."
4 5
6
Search PT/CLP 0
7
Pass All Cells
0
Table 21 Internal Register Map (Part 1 of 5)
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QRLWSLUFVH'
March 26, 2001
HXOD9 QRLWDFR/ ;(+ HPD1 WOXDIH' HPD1 WL% WL% VVHUGG$ UHWVLJH5
IDT77V012
Configuration 2 8002
0 1 2
Insert New Header Overwrite GFC Overwrite PT/ CLP Rx Move PT/ CLP Tx Move PT/ CLP Drop Cell
0 0 0
"Insert New Header. "0" do not replace existing header with new header from search, "1" replace existing cell header with the new header found in search." "Overwrite the GFC field with the new header value. "0" do not overwrite GFC field with new value, "1" overwrite GFC field with value found in search." "Overwrite PT/CLP fields in the new cell header. "0" do not overwrite PT/CLP fields of the original header with the value found in the search, "1" overwrite PT/CLP fields of the original header with the value found in the search." "Move the PT/CLP fields from the original header into the 4-byte TAG area. "0" do not move PT/CLP fields, "1" move PT/CLP fields." "Move the PT/CLP fields from the 4-byte TAG area to the cell header. "0" do not move PT/CLP fields, "1" move PT/CLP fields." "Selects action when PHY transmit FIFO is full. "0" stall pipeline, "1" drop cell." "Allow cells to be dropped on the receive UTOPIA interface. In-StreamTM cells are not affected by the condition of this bit, if they are being filtered on the receive UTOPIA interface. "0" pass cells received on the receive UTOPIA interface, "1" filter and drop data cells on the receive UTOPIA interface."
3 4 5 6
0 0 0
RxData Cell Fil- 0 ter
7 Table Offset 8003 5-0 7-6 Pin Control 8004 0 1 2 3
Not Used Search Table Offset Result Node Offset Override Pin Control Control A Control B EEPROM Mux Select 0x00 0 0 0 0 0 Offset pointer for search table. Divides memory into 4K x 32-bit blocks. Result node offset pointer. Divides memory into 64K x 32-bit blocks. "Enables writing to pin configurable registers. "0" pin configurable registers are read only, "1" pin configurable registers are read/write." "Stores condition of Control A pin. "0" CTRL_A = "0", "1" CTRL_A = "1"." "Stores condition of Control B pin. "0" CTRL_B = "0", "1" CTRL_B = "1"." "Indicates if the EEPROM interface will be connected to the internal logic or the EEPROM registers. "0" connected to internal logic, "1" connected to EEPROM registers." "EEPROM clock when EEPROM interface is connected to the EEPROM registers. "0" clock low, "1" clock high." "EEPROM chip select when EEPROM interface is connected to the EEPROM registers. "0" EEPROM interface is selected, "1" EEPROM interface is not selected." EEPROM output bus when EEPROM interface is connected to the EEPROM registers. EEPROM input bus when EEPROM interface is connected to the EEPROM registers.
4 5 6 7 Tx TAG 8005 2-0 3 4 7-5
EEPROM Clock 0 Out EEPROM Chip Select EEPROM Out EEPROM In Tx TAG Size Tx TAG Location Tx Add HEC Not Used 0 0 0
Defined by Number of bytes to remove from the transmit cell. pin Defined by "TAG location in transmit direction. "0" TAG is located at beginning of cell, "1" TAG is pin located at end of cell." Defined by "Add a HEC placeholder in the transmit direction. "0" do not add a HEC place holder, pin "1" add a HEC place holder."
Table 21 Internal Register Map (Part 2 of 5)
39 of 46
QRLWSLUFVH'
March 26, 2001
HXOD9 QRLWDFR/ ;(+ HPD1 WOXDIH' HPD1 WL% WL% VVHUGG$ UHWVLJH5
IDT77V012
Rx TAG and Mode Select
8006
2-0 3 4 5
Rx Tag Size Rx Remove HEC DPI Mode In-StreamTM Direction Init from EEPROM Not Used Phy Interrupt Mask Rx Null Mask
Defined by Number of bytes to add to received cell. pin Defined by "Remove HEC from cell. "do not remove HEC byte from cell, "1" remove HEC byte pin from cell." Defined by "Selects DRxCLK direction. "0" switch mode (output), "1" normal mode (input)." pin Defined by Indicates what interface the In-StreamTM cells will be filtered on. "0" input on transmit pin DPI interface and output on receive DPI interface, "1" input on receive UTOPIA interface and output on transmit UTOPIA interface. 0 "Four byte write from EEPROM to In-StreamTM Cell Header registers at reset. "0" do not write four byte value, "1" write four byte value to registers."
6 7 Notification Mask 8007 0
0
"Mask interrupt notification. "0" no Event Notification cell will be generated when a PHY interrupt occurs, "1" generate Event Notification cell when a PHY interrupt occurs." "Mask interrupt notification. "0" no Event Notification cell will be generated when a Rx Null pointer is detected, "1" generate Event Notification cell when a Rx Null pointer is detected." "Mask interrupt notification. "0" no Event Notification cell will be generated when a Tx Null pointer is detected, "1" generate Event Notification cell when a Tx Null pointer is detected."
1
0
2
Tx Null Mask
0
7-3 Status 8008 0 1 2 7-3 Timeout Status 8009 0
Not Used Interrupt Status 0 Rx Null Pointer Status Tx Null Pointer Status Not Used PHY Interrupt Timer 0 "Indicates that a PHY Interrupt occurred more than 25ms ago and the Status register has not been serviced. This bit is cleared by writing to the Status register. "0" no PHY interrupts detected, "1" PHY interrupt occurred more than 25ms ago and the Status register has not been serviced." "Indicates that a Rx Null pointer was encountered more than 25ms ago and the Status register has not been serviced. This bit is cleared by writing to the Status register. "0" no Rx Null pointers detected, "1" Rx Null pointer encountered more than 25ms ago and Status register has not been serviced." "Indicates that a Tx Null pointer was encountered more than 25ms ago and the Status register has not been serviced. This bit is cleared by writing to the Status register. "0" no Tx Null pointers detected, "1" Tx Null pointer encountered more than 25ms ago and Status register has not been serviced." 0 0 "Indicates that a PHY interrupt occurred. "0" no PHY interrupts detected, "1" a PHY interrupt has been detected on the PHYINT pin." "Indicates that a Rx Null pointer was encountered. "0" no Rx Null pointer has been detected, "1" Rx Null pointer has been detected." "Indicates that a Tx Null pointer was encountered. "0" no Tx Null pointer has been detected, "1" Tx Null pointer has been detected."
1
Rx Null Pointer Timer
0
2
Tx Null Pointer Timer
0
7-3
Not Used Table 21 Internal Register Map (Part 3 of 5)
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QRLWSLUFVH'
March 26, 2001
HXOD9 QRLWDFR/ ;(+ HPD1 WOXDIH' HPD1 WL% WL% VVHUGG$ UHWVLJH5
IDT77V012
Reset
800A
0 1
PHY Reset Search Table Reset
0 0
"PHY reset. "0" no PHY reset, "1" PHY reset (PHYRST signal will be asserted low for 16 system clock cycles)." "Writes Null pointers into Search Table. "0" do not write Null pointers into Search Table, "1" write Null pointers into Search Table (will reset back to zero once the operation is completed in approx. 1K to 12K SYSCLK cycles depending on the size of the Search Table). This value is obtained from the Null Pointer Address registers."
7-2 Null Pointer 800B Address Byte 2 1-0 7-2 Null Pointer 800C Address Byte 1 Null Pointer 800D Address Byte 0 In-StreamTM Cell Header Byte 3 In-StreamTM Cell Header Byte 2 In-StreamTM Cell Header Byte 1 In-StreamTM Cell Header Byte 0 In-StreamTM TAG Byte 3 In-StreamTM TAG Byte 2 In-StreamTM TAG Byte 1 In-StreamTM TAG Byte 0 Rx Null Pointer Header Byte 3 Rx Null Pointer Header Byte 2 Rx Null Pointer Header Byte 1 Rx Null Pointer Header Byte 0 Tx Null Pointer Header Byte 3 800E 7-0 7-0 7-0
Not Used Null Pointer [17:16] Not Used Null Pointer [15:8] Null Pointer [7:0] In-StreamTM Header [31:24] In-StreamTM Header [23:16] In-StreamTM Header [15:8] In-StreamTM Header [7:0] In-StreamTM TAG [31:24] In-StreamTM TAG [23:16] In-StreamTM TAG [15:8] In-StreamTM TAG [7:0] Rx Null Pointer Header [31:24] Rx Null Pointer Header [23:16] Rx Null Pointer Header [15:8] Rx Null Pointer Header [7:0] Tx Null Pointer Header [31:24] 0xFF 0xFF 0x00 Null pointer search tree address and value written in search tree. Null pointer search tree address and value written in search tree. Cell header for In-StreamTM programming cells. 0x3 Null pointer search tree address and value written in search tree.
800F
7-0
0x00
Cell header for In-StreamTM programming cells.
8010
7-0
0x01
Cell header for In-StreamTM programming cells.
8011
7-0
0xF0
Cell header for In-StreamTM programming cells.
8012 8013 8014 8015 8016 8017 8018 8019 801A
7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0
0x00 0x00 0x01 0xF0 NA NA NA NA NA
TAG added to In-StreamTM programming cells. TAG added to In-StreamTM programming cells. TAG added to In-StreamTM programming cells. TAG added to In-StreamTM programming cells. Header filtered on receive DPI interface. Header filtered on receive DPI interface. Header filtered on receive DPI interface. Header filtered on receive DPI interface. Header filtered on transmit DPI interface.
Table 21 Internal Register Map (Part 4 of 5)
41 of 46
QRLWSLUFVH'
March 26, 2001
HXOD9 QRLWDFR/ ;(+ HPD1 WOXDIH' HPD1 WL% WL% VVHUGG$ UHWVLJH5
IDT77V012
Tx Null Pointer Header Byte 2 Tx Null Pointer Header Byte 1 Tx Null Pointer Header Byte 0
801B 801C 801D
7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0
Tx Null Pointer Header [23:16] Tx Null Pointer Header [15:8] Tx Null Pointer Header [7:0]
NA NA NA
Header filtered on transmit DPI interface. Header filtered on transmit DPI interface. Header filtered on transmit DPI interface. Counter for cells received on the receive UTOPIA bus. Counter for cells received on the receive UTOPIA bus. Counter for cells received on the receive UTOPIA bus. Counter for cells received on the receive UTOPIA bus. Counter for cells transmitted on the transmit UTOPIA bus. Counter for cells transmitted on the transmit UTOPIA bus. Counter for cells transmitted on the transmit UTOPIA bus. Counter for cells transmitted on the transmit UTOPIA bus.
UTOPIA Rx Cell 801E Counter byte 3 UTOPIA Rx Cell 801F Counter byte 2 UTOPIA Rx Cell 8020 Counter byte 1 UTOPIA Rx Cell 8021 Counter byte 0 UTOPIA Tx Cell 8022 Counter byte 3 UTOPIA Tx Cell 8023 Counter byte 2 UTOPIA Tx Cell 8024 Counter byte 1 UTOPIA Tx Cell 8025 Counter byte 0
Rx Cell Counter 0x00 [31:24] Rx Cell Counter 0x00 [23:16] Rx Cell Counter 0x00 [15:8] Rx Cell Counter 0x00 [7:0] Tx Cell Counter 0x00 [31:24] Tx Cell Counter 0x00 [23:16] Tx Cell Counter 0x00 [15:8] Tx Cell Counter 0x00 [7:0]
Table 21 Internal Register Map (Part 5 of 5)
64K memory - 28 bits header lookup - Cell accounting 14000
12000
10000
Best Case
Number of connections
8000
6000
4000
Worst Case
2000
0
0
500
1000
1500
2000 2500 Number of search trees
3000
3500
Figure 47 Memory Usage for 9 Levels of Search
42 of 46
QRLWSLUFVH'
4000 4500
5347drw52
HXOD9 QRLWDFR/ ;(+ HPD1 WOXDIH' HPD1 WL% WL% VVHUGG$ UHWVLJH5
March 26, 2001
IDT77V012
128K memory - 28 bits header lookup - Cell accounting 18000 Best Case 16000
14000
12000
Number of connections
10000
8000 Worst Case 6000
4000
2000
0
0
500
1000
1500
2000 2500 Number of search trees
3000
3500
4000
4500
5347drw53
256K memory - 28 bits header lookup - Cell accounting 18000 Best Case 16000 Worst Case
14000
12000
Number of connections
10000
8000
6000
4000
2000
0
0
500
1000
1500
2000 2500 Number of search trees
3000
3500
4000
4500
5347drw54
Figure 48 Memory Usage for 9 Levels of Search (Continued)
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March 26, 2001
IDT77V012
64K memory - 32 bits header lookup - Cell accounting 14000
12000
10000
Number of connections
Best Case 8000
6000
4000 Worst Case 2000
0
0
500
1000
1500
2000 2500 Number of search trees
3000
3500
4000
4500
5347drw55
128K memory - 32 bits header lookup - Cell accounting 18000 Best Case 16000
14000
12000
Number of connections
10000
8000
6000
Worst Case
4000
2000
0
0
500
1000
1500
2000 2500 Number of search trees
3000
3500
4000
4500
5347drw56
Figure 49 Memory Usage for 11 Levels of Search
44 of 46
March 26, 2001
IDT77V012
256K memory - 32 bits header lookup - Cell accounting 18000 Best Case 16000
14000 Worst Case 12000
Number of connections
10000
8000
6000
4000
2000
0
0
500
1000
1500
2000 2500 Number of search trees
3000
3500
4000
4500
5347drw57
Figure 50 Memory Usage for 11 Levels of Search (Continued)
A2
Amax
A1
PP [ [ H]L6 \GR% QLS 3)4 FLWVDO3 QRLWDP URIQ, HJDNFD3 PP [ [ H]L6 \GR% QLS 3)4 FLWVDO3 QRLWDP URIQ, HJDNFD3 PP [ [ H]L6 \GR% QLS 3)4 FLWVDO3 QRLWDP URIQ, HJDNFD3 PP [ [ H]L6 \GR% QLS 3)4 FLWVDO3 QRLWDP URIQ, HJDNFD3
HD D
Symbol Dimension in Millimeters
73
Dimension in Inches1 Min
(0.784) (0.784)
108 109
Min
72
Norm
20 20
Max
20.1 20.1 1.7
Norm
(0.787) (0.787)
Max
(0.791) (0.791) (0.066)
E D
19.9 19.9
f
A A1 A2
b
0.1 1.3 1.4 0.5 0.15 0.1 0o 0.3 0.5 1 0.5 21.6 21.6 22 22 12o 12o 0.2 0.2 for reference 22.4 22.4 (0.851) (0.851) 0.2 0.125 0.3 0.175 10o 0.7 (0.006) (0.004) (0o) (0.012) 1.5 (0.052)
(0.004) (0.055) (0.020) (0.008) (0.005) (0.011) (0.006) (10o) (0.020) (0.039) (0.020) (0.866) (0.866) (12o) (12o) (0.008) (0.008) (0.881) (0.881) (0.027) (0.059)
E
HE
f b C q L L1 L2
Index 144 37
HE HD q2
R1 R
1
36
q2
q3 R R1
1.
q q3 L2 L1 L C
5347drw58
45 of 46
March 26, 2001
IDT77V012
\ URWVL+ WQHPXFR' WHHK6 DWD' \ URWVL+ WQHPXFR' WHHK6 DWD' \ URWVL+ WQHPXFR' WHHK6 DWD'
QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range (Blank) Industrial DA PQFP (144-pin) 155 4-bit Port Bandwidth in Mbps L Low Power 77V012 DATA PATH INTERFACE (DPI) TO UTOPIA LEVEL 1 HEADER TRANSLATION DEVICE
5347drw58
9/07/99 10/26/99 1/27/00 02/03/00 03/03/00 09/12/00 10/15/00 12/18/00 03/26/01
Initial Public Release Added Commercial temperature range and ordering information. Added text to In-StreamTM section for 1 to 31-byte internal register access. Fixed typos in In-StreamTM text. Deleted Commercial temperature range and ordering information, corrected maximum delay values for back to back cells, updated Utility bus write timing, corrected tables 25 and 32 In-StreamTM Direction. Corrected In-StreamTM data field description and drawing for Notification cells. Corrected text and drawings for In-StreamTM Discovery/Identify cells. Converted from Preliminary to Final. Added overbars to pin EECS; in Figure 12, changed READ to RD; in Note for Figure 46, added overbar to pins CE and CS1.
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com
for Tech Support: email: sarhelp@idt.com phone: 408-492-8208
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
46 of 46
March 26, 2001

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